CDR Saddle-Point Lock Detection With Fast-Phase Correction
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Solution Overview
Problem
High-speed serial link communication systems face challenges in clock and data recovery, particularly in avoiding saddle-point locking events that lead to prolonged lock times and reduced data transmission efficiency due to noise and signal impairments.
Innovation Solution
The method involves using a primary clock and data recovery (CDR) loop with a fast-phase lock module to detect saddle-point locking by determining transitions in a sampling triplet, providing a trigger signal for fast-phase lock operations, and iteratively adjusting the phase correction magnitude to minimize clock recovery errors, effectively shifting the sampling phase to avoid metastable states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional CDR loop is used for clock and data recovery, then the system can maintain basic lock functionality, but saddle-point locking events occur leading to prolonged lock times and reduced data transmission efficiency
Solution Approach 1:
The patent applies preliminary action by detecting saddle-point locking conditions before they cause prolonged lock times. The system monitors phase error characteristics and transitions to detect early signs of saddle-point locking, then preemptively activates fast-phase lock operations to correct the condition before it fully develops, thereby preventing the time loss that would otherwise occur.
Solution Approach 2:
The patent implements feedback by continuously monitoring the CDR loop's phase error and transition signals to detect saddle-point locking conditions. The detection mechanism provides real-time feedback about the loop's state, and when saddle-point locking is detected, the system feeds back a trigger signal to activate fast-phase lock correction, creating a closed-loop control system that actively prevents prolonged lock times.
2Adaptability or versatility
If noise and signal impairments are present in the transmission medium, then real-world communication conditions are reflected, but saddle-point locking events are triggered leading to extended lock times
Solution Approach 1:
The patent applies preliminary anti-action by preparing the CDR loop to counteract the harmful effects of noise and signal impairments before they cause saddle-point locking. The system continuously monitors for conditions that precede saddle-point locking (such as specific transition patterns in the presence of noise) and activates corrective fast-phase lock operations in advance, preventing the reliability degradation that would otherwise result from noise-induced saddle-point locking events.
3Productivity
If the CDR loop operates at high data transmission speeds, then data capacity requirements are met, but saddle-point locking events have more severe impact on transmission efficiency
Solution Approach 1:
The patent applies the skipping principle by implementing fast-phase lock operations that rapidly traverse the phase correction space when saddle-point locking is detected. Instead of allowing the CDR loop to slowly drift or stagnate in the metastable saddle-point condition, the system rushes through the correction process by applying larger phase adjustments and reducing the number of iterations needed to escape the saddle-point, thereby minimizing the time loss at high transmission speeds.
Data Source
AI summary
The present disclosure relates to a method and apparatus for detecting clock and data recovery loop saddle-point locking in an electronic circuit. Embodiments may include receiving a signal at a primary clock and data recovery (“CDR”) loop associated with the electronic circuit and processing the signal using at least one of a first order CDR loop and a second order CDR loop included within the primary CDR loop. Embodiments may further include determining whether a fast-phase lock module is required, wherein determining includes determining two transitions in a sampling triplet. If it is determined that the fast-phase lock module is required, embodiments may include providing a trigger signal to the fast-phase lock module. Embodiments may further include receiving the trigger signal at the fast-phase lock module associated with the electronic circuit and performing a fast-phase lock operation on the signal.