Clock Synchronization Using PWM Phase-Difference Feedback
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Solution Overview
Problem
Conventional electronic systems using phase-locked loops (PLL) for clock signal synchronization are inefficient, requiring significant time and unable to adapt to different operation states, leading to suboptimal synchronization performance.
Innovation Solution
A clock generating device comprising a clock generating unit and a computing unit that utilizes interrupt signals to synchronize a pulse-width modulation signal with a synchronization signal by adjusting a control signal based on synchronization period and phase difference, allowing for rapid synchronization and adaptive control through software adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hardware-based phase-locked loop (PLL) is used for clock signal synchronization, then the synchronization process can be implemented in hardware, but the synchronization time is significantly extended and cannot be controlled according to different operation states
Solution Approach 1:
The patent implements dynamic synchronization by allowing the synchronization period to be adjusted according to different operation states of the electronic system. The computing unit can dynamically modify the control signal parameters based on real-time system state, enabling the synchronization process to adapt to varying operational requirements rather than being fixed in hardware.
Solution Approach 2:
The patent changes the synchronization approach by modifying control signal parameters (such as pulse width modulation duty cycle) based on detected phase differences and synchronization periods. The computing unit adjusts these parameters dynamically to achieve synchronization within 2 periods of the synchronization signal, significantly reducing synchronization time compared to traditional hardware PLL.
2Productivity
If hardware-based phase-locked loop (PLL) is used for clock signal synchronization, then the synchronization can be performed, but the synchronization process consumes significant time and cannot be controlled adaptively
Solution Approach 1:
The patent implements a feedback mechanism where the computing unit continuously monitors the phase difference between the synchronization signal and the generated clock signal. Based on this feedback, the system dynamically adjusts the control signal parameters to minimize phase difference and achieve synchronization. This closed-loop feedback enables both rapid synchronization and adaptive control according to different operation states.
Solution Approach 2:
The patent replaces the traditional hardware-based mechanical PLL system with a software-implemented synchronization mechanism in the computing unit. This substitution allows for more flexible and rapid adjustment of synchronization parameters, achieving synchronization within 2 periods of the synchronization signal while maintaining adaptability to different operation states through software control.
Data Source
AI summary
A clock generating device is disclosed. The clock generating device includes a clock generating unit, for counting a synchronization period of a synchronization signal, generating a first interrupt signal according to the synchronization signal, generating a pulse-width modulation signal according a control signal, counting a phase difference between the synchronization signal and the pulse-width modulation signal, and generating a second interrupt signal according to the pulse-width modulation signal; and a computing unit, for acquiring the synchronization period according to the first interrupt signal, acquiring the phase difference according to the second interrupt signal, and adjusting the control signal according to the synchronization period, a modulation period of the pulse-width modulation signal and the phase difference.