CDR Clock Phase Resynchronization for Data Stream Drift
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional edge-based clock and data recovery (CDR) circuits face challenges in maintaining optimal sampling phase alignment due to data stream drift, especially in asymmetric data eyes, and require precise quadrature relationships between data and edge clocks, which are difficult to achieve in practice, leading to compromised noise margins.
Innovation Solution
The proposed CDR circuit employs a phase selector to generate data and edge clocks, which are synchronized during an initialization phase and can be re-synchronized during normal operation by adjusting the edge clock to maintain an approximate quadrature phase relationship, allowing optimal sampling even in the presence of data stream drift without requiring precise quadrature alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional edge-based CDR circuits use precise quadrature relationship between data and edge clocks, then optimal sampling phase alignment can be achieved, but the system becomes sensitive to data stream drift and difficult to implement in practice
Solution Approach 1:
The patent implements dynamic phase adjustment by allowing the edge clock to be resynchronized during normal operation based on detected data stream drift. The system transitions from a static precise quadrature relationship to a dynamic adaptation mechanism that maintains approximate quadrature while compensating for drift, resolving the contradiction between precision and robustness
Solution Approach 2:
The system changes the operational parameter from requiring precise quadrature phase relationship to accepting approximate quadrature with dynamic adjustment. By modifying the phase relationship parameter from fixed-precision to flexible-adaptive, the system achieves both good sampling alignment and robustness against data stream drift
2Measurement precision
If conventional CDR circuits require precise quadrature alignment between clocks, then optimal sampling can be achieved, but the device complexity and difficulty of implementation increase
Solution Approach 1:
The patent applies partial action by requiring only approximate quadrature alignment rather than precise alignment. This relaxation of the precision requirement reduces implementation complexity while still achieving sufficient sampling performance, eliminating the need for complex precision synchronization mechanisms
Solution Approach 2:
The system implements self-service through automatic resynchronization of the edge clock during normal operation. The CDR circuit automatically detects and corrects phase drift without external intervention, simplifying the overall system architecture by eliminating the need for complex external synchronization control
3Reliability
If conventional edge-based CDR circuits are used, then clock recovery can be achieved, but noise margins are compromised due to difficulty in maintaining precise quadrature relationship
Solution Approach 1:
The patent implements feedback by continuously monitoring the phase relationship between data and edge clocks and automatically adjusting the edge clock phase to maintain approximate quadrature. This closed-loop feedback mechanism ensures optimal sampling phase alignment is maintained, maximizing noise margins while simplifying operation through automatic adjustment
Data Source
AI summary
Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.