Receiver Clock Phase Alignment for Live DFE Sampling
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Solution Overview
Problem
High-speed serial receivers are sensitive to process variations, voltage drift, and temperature drift, leading to phase mismatches between clock signals that affect their operation and data recovery accuracy.
Innovation Solution
A receiver with live clock phase calibration that includes a main DFE data sampler and an adaptive DFE data sampler, where the phases of the clock signals are aligned through a calibration process during live data traffic, using phase adjustment circuits and multiplexers to selectively use either the main or adaptive digital data for output, thereby correcting phase errors without interrupting the data stream.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed serial receivers operate at increased signaling rates, then data transmission speed is improved, but sensitivity to process variations, voltage drift, and temperature drift increases causing phase mismatches
Solution Approach 1:
The patent performs phase calibration in advance during initialization or low-traffic periods to establish accurate phase relationships between clock signals before high-speed data transmission begins, preventing phase mismatches from degrading performance during critical operation
Solution Approach 2:
The patent implements continuous phase error detection and calibration mechanisms that monitor phase relationships during operation and automatically adjust clock phases to maintain synchronization, using feedback from phase error measurements to correct drift in real-time
2Productivity
If phase calibration is performed during live data traffic, then data stream continuity is maintained, but calibration accuracy may be reduced due to ongoing data transmission
Solution Approach 1:
The patent divides the calibration process into separate stages or uses different calibration methods for different conditions, such as performing coarse calibration during initialization and fine calibration during operation, or using dedicated calibration data patterns separated from normal data traffic
Solution Approach 2:
The patent introduces calibration data patterns or test signals as intermediaries that carry phase calibration information through the data path without disrupting the actual data stream, allowing phase measurement and adjustment using controlled test patterns while maintaining normal operation
Data Source
AI summary
A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.