CDR Loop Acquisition Using Mislock Feedback for Large Frequency Offsets
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Solution Overview
Problem
Serializer/deserializer (SerDes) applications face performance degradation due to large frequency offsets between transmitter and receiver clocks, which existing clock and data recovery (CDR) systems struggle to track, leading to increased power consumption, hardware complexity, and cost when using rotational frequency detection algorithms and eye scope latches.
Innovation Solution
A method that initializes and adjusts the integral register in a digital loop filter of the CDR system by counting mislock events to acquire the reference clock signal, eliminating the need for an eye scope latch and reducing power consumption, hardware complexity, and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a rotational frequency detection (RFD) algorithm with an eye scope latch is used to track frequency offsets, then the CDR system can acquire the transmitter clock, but power consumption, hardware complexity and cost substantially increase
Solution Approach 1:
The patent extracts and eliminates the eye scope latch from the CDR system by implementing a digital solution using a mislock counter and integral register adjustment mechanism. This removes the problematic analog hardware while preserving the frequency offset tracking capability through digital counting and register adjustment operations.
Solution Approach 2:
The patent replaces the mechanical/analog eye scope latch with a digital system consisting of a mislock counter, phase frequency detector, and integral register adjustment logic. This substitution transitions from analog hardware to digital processing, reducing hardware complexity while maintaining functionality.
2Reliability
If a rotational frequency detection (RFD) algorithm with an eye scope latch is used to track frequency offsets, then the CDR system can acquire the transmitter clock, but power consumption substantially increases
Solution Approach 1:
The patent removes the power-hungry eye scope latch hardware and replaces it with a digital mislock counter and register adjustment system that consumes significantly less power while achieving the same frequency offset tracking objective.
Solution Approach 2:
The CDR system uses its own existing digital components (phase frequency detector, integral register, mislock counter) to perform the frequency offset tracking function that previously required external analog hardware, making the system more energy-efficient and self-sufficient.
3Reliability
If an eye scope latch is used to track frequency offsets, then the CDR system can acquire the transmitter clock, but calibration of the latch becomes a stringent necessity
Solution Approach 1:
The patent eliminates the eye scope latch that required stringent calibration by replacing it with a digital mislock counter system that automatically tracks frequency offsets without requiring manual calibration procedures, simplifying manufacturing and testing.
Solution Approach 2:
The system performs automatic frequency offset tracking using the mislock counter and integral register adjustment without requiring external calibration equipment or procedures, making the system self-calibrating and easier to manufacture.
4Reliability
If the integral register value is not adjusted in response to mislock events, then the CDR loop structure remains simple, but the CDR system cannot acquire frequency offsets within its theoretical capability
Solution Approach 1:
The patent implements a feedback mechanism where the mislock counter monitors CDR loop performance and automatically adjusts the integral register value in response to detected mislock events, enabling the system to acquire frequency offsets that would otherwise be beyond its theoretical capability while maintaining a relatively simple loop structure.
Data Source
AI summary
A method for facilitating acquisition of a received reference clock signal in a CDR system includes steps of: initializing an integral register in a digital loop filter of the CDR system by setting a current value of the integral register to a first value; determining a number of mislock events occurring in a CDR loop of the CDR system, a mislock event being indicative of an unlocked state of the CDR loop; adjusting the current value of the integral register, when the number of mislock events is non-zero, by a second value to generate a new current value, the second value being a function of a negation of the current value of the integral register; and repeating the steps of determining the number of mislock events and adjusting the current value of the integral register until the number of mislock events is zero.