Dual-Loop Clock Recovery for High-Speed Receiver Sampling
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Solution Overview
Problem
Conventional digital systems face limitations in data transmission interconnection between integrated circuits, particularly in accurately recovering clock signals at higher data transmission speeds, which affects data reception accuracy.
Innovation Solution
The implementation of a receiver with multiple phase control loops, including edge and data samplers, and phase controllers that utilize edge and data transition information to generate and adjust clock signals, enhancing clock and data recovery through dual phase control loops for improved accuracy and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single phase control loop is used for clock recovery, then the device complexity is reduced, but the measurement precision of clock signal phase deteriorates at higher data transmission speeds
Solution Approach 1:
The patent divides the clock recovery function into two separate phase control loops: a first phase control loop that uses edge sampling to generate a first clock signal, and a second phase control loop that uses data sampling to generate a second clock signal. This segmentation allows each loop to specialize in different aspects of clock recovery, improving overall accuracy without requiring a single overly complex loop to handle all functions.
Solution Approach 2:
The patent introduces a dual-loop architecture that operates in parallel dimensions, combining edge-based phase detection with data-based phase detection. This dimensional expansion from a single-loop to a multi-loop system enables the receiver to capture phase information from multiple sources, thereby improving measurement precision through diversified phase estimation approaches.
2Productivity
If higher data transmission speeds are used, then the productivity of the system is improved, but the reliability of data reception deteriorates due to clock recovery inaccuracies
Solution Approach 1:
The patent implements feedback mechanisms in both phase control loops where the received signal is continuously sampled and compared against expected transitions. The first loop uses edge detection feedback to adjust the first clock signal phase, while the second loop uses data sampling feedback to adjust the second clock signal phase. This continuous feedback ensures accurate clock synchronization even at high transmission speeds, maintaining data reception reliability.
Solution Approach 2:
The patent changes the operational parameters of the clock recovery system by operating two loops with different sampling strategies (edge sampling vs. data sampling) and different phase detection methods. This parameter diversification allows the system to adapt to high-speed transmission conditions where single-parameter approaches fail, thereby maintaining both high productivity and reliability.
3Speed
If edge sampling is used for phase detection, then the response speed to data transitions is improved, but the precision in determining optimal data sampling points deteriorates
Solution Approach 1:
The patent segments the phase detection function into two specialized detectors: an edge detector that excels at rapid response to transitions, and a data sampler that excels at precise timing determination. The edge detector quickly identifies transition moments to provide rapid phase adjustment, while the data sampler independently determines optimal sampling points with high precision. This segmentation allows each component to optimize for its specific function without compromise.
Solution Approach 2:
The patent adds a temporal dimension to phase detection by using two different sampling moments: edge transitions (for speed) and data center points (for precision). This dimensional approach allows the system to simultaneously capture rapid transitions and precise timing information, resolving the contradiction between response speed and timing accuracy through multi-temporal sampling.
4Measurement precision
If data sampling is used for phase detection, then the accuracy in determining data intervals is improved, but the response speed to phase changes deteriorates
Solution Approach 1:
The patent segments the clock recovery function into two parallel loops with different response characteristics. The second loop using data sampling provides high precision timing for data intervals, while the first loop using edge sampling provides rapid response to phase changes. This segmentation allows the precision-oriented data sampling loop to operate without being burdened by speed requirements, as the speed-critical function is handled by the edge sampling loop.
Solution Approach 2:
The patent merges the outputs of two phase control loops to generate the final recovered clock signal. The first loop's rapid phase adjustments and the second loop's precise timing information are combined, allowing the system to achieve both fast response and high accuracy. This merging enables the precision-oriented data sampling approach to benefit from the speed enhancements provided by edge sampling without sacrificing its timing accuracy.
Data Source
AI summary
A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.