Reconfigurable Multimedia Receiver Circuit for Shared HDMI DP Clocks
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Solution Overview
Problem
Conventional electronic devices equipped with HDMI, MHL, and DP receiving circuits require three independent circuits, leading to high hardware costs due to redundant components and complex designs.
Innovation Solution
A multimedia interface receiving circuit that shares circuit elements and selectively configures signal processing channels to function as either an HDMI, MHL, or DP receiving circuit, utilizing a phase-locked loop (PLL) and signal processing channels with phase detecting circuits to adapt to different interface standards, thereby reducing hardware costs and design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If three independent receiving circuits (HDMI, MHL, DP) are provided simultaneously, then compatibility with different multimedia interfaces is improved, but hardware cost and device complexity increase
Solution Approach 1:
The patent implements a universal receiving circuit that can operate in three different modes (HDMI receiving mode, MHL receiving mode, and DP receiving mode) by dynamically reconfiguring the same hardware components. The circuit shares analog front-end circuits, phase-locked loops, and signal processing channels across all three interface standards, allowing one circuit to perform multiple functions that previously required three separate circuits.
Solution Approach 2:
The patent employs dynamic reconfiguration of circuit connections and signal routing based on the detected interface type. Control circuits dynamically adjust the configuration of phase-locked loops, enable or disable specific signal processing channels, and re route differential signals to appropriate processing paths, transforming static hardware into a dynamically adaptable system.
2Adaptability or versatility
If three independent receiving circuits are provided, then support for multiple interface standards is improved, but the quantity of hardware components increases
Solution Approach 1:
The patent merges the functionality of three separate receiving circuits into a single integrated circuit. Shared components include analog front-end circuits that process differential signals, common phase-locked loop circuits for clock recovery, and multiplexed signal processing channels that can handle data from any of the three interface standards, thereby reducing the total quantity of hardware components.
Solution Approach 2:
Each major circuit block is designed to be universal rather than dedicated to a single interface standard. The analog front-end circuits can process differential signals from any interface, the phase-locked loops can recover clocks from different signal formats, and the signal processing channels can be dynamically allocated to handle data streams from HDMI, MHL, or DP sources.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces hardware costs and simplifies circuit design by enabling the multimedia interface receiving circuit to seamlessly switch between HDMI, MHL, and DP configurations, maintaining compatibility while minimizing redundant components.
Implementation Method 1
The PLL includes a phase frequency detector. Each of the four signal processing channels includes a phase detecting circuit
Implementation Method 2
Each of the three signal processing channels adjusts a phase of the locked clock signal according to the input signal to generate a sampling clock signal for the use of the phase detecting circuit
Data Source
AI summary
A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition Multimedia Interface (HDMI) configuration, one of the processing channels is disabled, and the PLL provides a locked clock signal to the other three processing channels. Each of the other three processing channels adjusts the phase of the locked clock signal to generate a sampling clock signal. In a DisplayPort (DP) configuration, the PLL changes to connect to the phase detecting circuit of one of the four signal processing channels to form an analog clock data recovery (ACDR) circuit to generate a fundamental clock signal. Each of the three other processing channels adjusts the phase of the fundamental clock signal to generate the sampling clock signal.