CDR Gain Switching for Faster Link Synchronization Recovery
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Solution Overview
Problem
High-speed data transfer interfaces face challenges in maintaining synchronization due to defects in Clock Data Recovery (CDR) circuits, leading to communication interruptions caused by noise and inefficient synchronization establishment processes.
Innovation Solution
A method and device that includes a CDR circuit with a synchronization retry process, where if synchronization is not established within a predetermined time, the circuit is reset or its gain parameter is adjusted to improve responsiveness, thereby preventing connection failures and maintaining synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CDR circuit uses a fixed gain parameter for synchronization, then the circuit structure is simple, but the synchronization establishment time is too long causing connection failures
Solution Approach 1:
The CDR circuit dynamically adjusts its gain parameter based on synchronization status. During the synchronization establishment phase, the circuit operates with a first gain parameter that provides higher responsiveness to quickly establish synchronization. Once synchronization is achieved, it switches to a second gain parameter for normal operation. This dynamic parameter adjustment resolves the contradiction by allowing fast synchronization establishment without compromising normal operational stability.
Solution Approach 2:
The invention changes the gain parameter of the CDR circuit from a fixed value to a variable value that depends on the synchronization state. By switching between different gain parameters (first gain parameter during synchronization, second gain parameter during normal operation), the system optimizes both the speed of synchronization establishment and the stability of normal data transfer, thereby preventing connection failures while maintaining operational reliability.
2Speed
If the CDR circuit increases response sensitivity for large phase differences, then synchronization establishment is faster, but noise susceptibility increases causing synchronization loss
Solution Approach 1:
The CDR circuit dynamically adjusts its gain parameter based on the operational phase. During synchronization establishment when phase differences are large, the circuit uses a higher gain parameter to achieve fast response. After synchronization is achieved and phase differences become small, the circuit switches to a lower gain parameter to reduce noise susceptibility and prevent synchronization loss. This dynamic adaptation resolves the contradiction between response speed and noise immunity.
Solution Approach 2:
The invention implements parameter changes by switching between different gain values based on synchronization status. The first gain parameter is optimized for fast acquisition during large phase differences, while the second gain parameter is optimized for stable tracking during small phase differences. This parameter switching mechanism allows the system to achieve both fast synchronization establishment and robust noise rejection during normal operation.
3Loss of time
If the CDR circuit uses high gain for fast synchronization, then synchronization establishment is quicker, but connection stability during data transfer deteriorates
Solution Approach 1:
The CDR circuit employs dynamic gain parameter switching to address the contradiction between fast synchronization and stable connection. During the initial synchronization phase, the circuit uses a higher gain parameter to quickly reduce phase differences and establish synchronization within the detection time. Once synchronized, the circuit transitions to a lower gain parameter that provides better noise filtering and maintains connection stability during prolonged data transfer operations.
Solution Approach 2:
The invention changes the gain parameter from a single fixed value to multiple context-dependent values. The first gain parameter accelerates synchronization establishment by increasing response sensitivity during the critical detection period. The second gain parameter maintains connection stability by reducing noise amplification during normal data transfer. This parameter change strategy resolves the contradiction by optimizing performance for each operational phase.
Data Source
AI summary
A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.