SERDES Receiver Frequency Acquisition Without External Reference Clocks
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Solution Overview
Problem
Existing data communication systems, particularly SERDES receivers, are inadequate for high-data applications due to high power consumption and large device area requirements, as they rely on external reference clocks and phase-lock loops, which are costly and inefficient.
Innovation Solution
A SERDES receiver design that eliminates the need for external reference clocks and phase-lock loops by using an on-chip oscillator to generate clock signals, with a digital control module to set frequency and an analog control module to adjust phase, along with data samplers and early/late detection logic to determine the correct sampling frequency through a frequency sweep process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external reference clocks and phase-lock loops are used in SERDES receivers, then clock signal accuracy is improved, but power consumption increases and device area increases
Solution Approach 1:
The patent extracts and eliminates the external reference clock and phase-lock loop components from the SERDES receiver system. By removing these power-consuming external components and replacing them with an integrated on-chip oscillator, the invention reduces power consumption while maintaining acceptable clock accuracy for the application
Solution Approach 2:
The patent merges the clock generation function directly into the SERDES receiver chip by integrating an on-chip oscillator. This consolidation eliminates the need for separate external reference clock circuits and phase-lock loops, reducing both device area and power consumption while providing the necessary clock signal for data sampling
2Measurement precision
If external reference clocks and phase-lock loops are used in SERDES receivers, then clock signal accuracy is improved, but device area increases
Solution Approach 1:
The patent extracts and eliminates the external reference clock and phase-lock loop components from the SERDES receiver system. By removing these external components and replacing them with an integrated on-chip oscillator, the invention reduces device area while maintaining acceptable clock accuracy
Solution Approach 2:
The patent merges the clock generation function directly into the SERDES receiver chip by integrating an on-chip oscillator. This consolidation eliminates the need for separate external reference clock circuits and phase-lock loops, reducing device area while providing the necessary clock signal
3Measurement precision
If frequency sweep process is implemented to determine target sampling frequency, then sampling accuracy is improved, but acquisition time increases
Solution Approach 1:
The patent implements a frequency sweep process during the initialization or calibration phase to preliminarily determine the optimal sampling frequency before normal data transmission begins. This preliminary action ensures accurate sampling frequency selection while limiting the time penalty to only the setup phase, not the ongoing data transmission
Solution Approach 2:
The frequency sweep process uses feedback from early/late detection logic to monitor sampling quality at different frequencies and automatically identify the optimal target frequency. This feedback mechanism ensures accurate sampling frequency selection while the sweep is confined to a predetermined frequency range to limit acquisition time
Data Source
AI summary
The present invention is directed to data communication. More specifically, embodiments of the present invention provide a method for acquiring sampling frequency by sweeping through a predetermined frequency range, performing data sampling at different frequencies within the predetermined frequency range, and determining a target frequency for sampling data based on a maximum early peak frequency and a maximum late peak frequency. There are other embodiments as well.