SERDES Receiver Frequency Sweep Without External PLL Clocks
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Solution Overview
Problem
Existing data communication systems, particularly SERDES receivers, are inadequate for high-data applications due to high power consumption and large device area requirements, as they rely on external reference clocks and phase-lock loops, which are costly and inefficient.
Innovation Solution
A SERDES receiver design that eliminates the need for external reference clocks and phase-lock loops by using an on-chip oscillator to generate clock signals, with a digital control module to set frequency and an analog control module to adjust phase, coupled with data samplers and early/late detection logic to determine the correct sampling frequency through a frequency sweep process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external reference clocks and phase-lock loops are used in SERDES receivers, then frequency accuracy and stability are improved, but power consumption and device area increase
Solution Approach 1:
The patent extracts and eliminates the external reference clock and phase-lock loop components from the SERDES receiver system. By removing these power-consuming external components and replacing them with an on-chip oscillator, the invention reduces power consumption while maintaining frequency acquisition capability through a simplified architecture that uses only essential frequency detection and adjustment circuitry.
2Measurement precision
If external reference clocks and phase-lock loops are used in SERDES receivers, then frequency accuracy and stability are improved, but device area increases
Solution Approach 1:
The patent removes the external reference clock and phase-lock loop components that occupy significant device area. By integrating only an on-chip oscillator and minimal frequency detection circuitry, the invention achieves frequency acquisition functionality with a dramatically reduced device footprint, eliminating the need for large external clock distribution networks and complex phase-lock loop circuits.
Solution Approach 2:
The patent merges the frequency generation and frequency detection functions into a single integrated on-chip system. The on-chip oscillator provides both the reference frequency and the adjustable sampling clock, while the frequency detection logic directly monitors and adjusts the oscillator frequency, eliminating the need for separate external reference clocks and phase-lock loop circuits.
3Adaptability or versatility
If frequency sweep and detection is performed to determine target sampling frequency, then adaptability to frequency variations is improved, but acquisition time increases
Solution Approach 1:
The patent implements a direct frequency sweep method that rapidly tests discrete frequency points rather than performing gradual phase adjustments. The frequency detection logic quickly identifies the target frequency by sweeping through a predetermined range and detecting early/late peaks, achieving frequency acquisition in minimal time without the prolonged convergence period required by traditional phase-lock loops.
Data Source
AI summary
The present invention is directed to data communication. More specifically, embodiments of the present invention provide a method for acquiring sampling frequency by sweeping through a predetermined frequency range, performing data sampling at different frequencies within the predetermined frequency range, and determining a target frequency for sampling data based on a maximum early peak frequency and a maximum late peak frequency. There are other embodiments as well.