Auxiliary Common Line for FFS LCD Aperture Ratio

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Solution Overview

Problem

The existing array substrates for fringe field switching (FFS) mode LCD devices face challenges in maximizing the aperture ratio due to the need for separation between gate lines, common lines, and pixel electrodes, which reduces the length of the pixel electrode and makes it difficult to inspect for electrical shorts.

Innovation Solution

The introduction of an auxiliary common line parallel to the gate lines allows for the removal of the distance between the gate line and the common line, enhancing the aperture ratio and enabling inspection of shorts, while the pixel electrode is positioned on the uppermost layer and the common electrode is formed on the data lines, allowing for both fringe field switching and in-plane switching driving.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the gate line, common line, and pixel electrode are simultaneously formed with certain separation to prevent electrical short, then electrical reliability is improved, but the aperture ratio is reduced

Engineering Contradiction:
Improveelectrical reliabilityVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent divides the formation process into sequential stages: first forming the gate line and pixel electrode with insulation, then forming the common line separately. This segmentation allows each component to be optimized independently, eliminating the need for separation between gate line and common line while maintaining electrical reliability through the insulating layer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The insulating layer is formed preliminarily between the gate line and pixel electrode before forming the common line. This preliminary action ensures electrical isolation is already in place, allowing the common line to be positioned closer to the gate line without risk of short circuit, thereby increasing the aperture ratio.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the pixel electrode length is reduced due to separation requirements, then electrical short prevention is improved, but the light blocking area increases

Engineering Contradiction:
Improveshort circuit preventionVSAvoidluminance
Core Design Contradiction:
ReliabilityVSIllumination intensity

Solution Approach 1:

The patent segments the electrode formation into distinct stages with the pixel electrode formed first and extended to the substrate edge, then the common line formed separately. This allows the pixel electrode to achieve maximum length without being constrained by common line positioning, reducing light blocking while maintaining short circuit prevention through the insulating layer.

Inventive Principle:
Principle #1Segmentation

3Area of stationary object

If the gate line and common line are positioned closer to increase aperture ratio, then light transmission is improved, but electrical short risk increases

Engineering Contradiction:
Improveaperture ratioVSAvoidelectrical isolation
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The insulating layer is applied preliminarily between the gate line and pixel electrode before the common line is formed. This preliminary insulation action enables the gate line and common line to be positioned closer together for maximum aperture ratio while the pre-formed insulating layer maintains electrical isolation and prevents short circuits.

Inventive Principle:
Principle #10Preliminary action

4Ease of manufacture

If the common line is formed after the gate line and pixel electrode, then manufacturing flexibility is improved, but process complexity increases

Engineering Contradiction:
Improvemanufacturing flexibilityVSAvoidfabrication process
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent segments the electrode formation into three distinct manufacturing steps: (1) forming gate line and pixel electrode with insulating layer, (2) forming data lines and TFTs, (3) forming common line. This segmentation provides manufacturing flexibility to optimize each step independently while the systematic progression keeps process complexity manageable through clear stage separation.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration increases the aperture ratio by eliminating the need for distance between the gate line and the common line, allows for effective inspection of shorts, and maximizes the area of the pixel electrode, enhancing the overall performance and screen quality of the LCD device.

Implementation Method 1

a driving principle of an LCD device uses optical anisotropy and polarization qualities of liquid crystal

Methodology Applied
Scientific EffectOptical anisotropy: Anisotropy

Implementation Method 2

a driving principle of an LCD device uses optical anisotropy and polarization qualities of liquid crystal

Methodology Applied
Scientific EffectPolarization: Polarisation

Implementation Method 3

The FFS technique features that there is no color shift by precisely controlling liquid crystal

Methodology Applied
Scientific EffectFringe field switching: Electric Field

Data Source

PatentUS9171871B2Method for fabricating array substrate for FFS mode liquid crystal display device
Publication Date: 2015.10.27 LG DISPLAY CO LTD
  • US9171871B2 patent drawing
  • US9171871B2 patent drawing
  • US9171871B2 patent drawing

AI summary

An array substrate for a field switching mode liquid crystal display device and a fabrication method thereof are provided. The array substrate for an FFS mode LCD device includes: a plurality of gate lines formed on the substrate; a plurality of data lines arranged to cross the gate lines; a common line formed at the subpixel regions of the substrate; an auxiliary common line formed on the common line; TFTs formed at crossings of the gate lines and the data lines; a protective film formed on the substrate; and a pixel electrode and a common electrode formed on the protective film and connected with the TFTs and the auxiliary common line, respectively.