Solid-State Devices TRIZ Cases

Vertical capacitor stacking increases storage capacitance without expanding the aperture ratio.

A display substrate incorporates a dummy line positioned above signal lines to shield conductive traces during peripheral processing.

Aluminum alloy electrodes with nickel and silicon prevent metal diffusion into active layers, reducing contact resistance.

An integrated half-transmitting cone reflector reduces lateral emission volume by shortening the scattering distance between the chip and reflective surface.

A plated conductive material connects transparent electrodes to aluminum lines without direct contact.

A MEMS vacuum sensor uses a motion beam and electrodes to measure internal pressure via capacitance changes.

Applying positive bias to the upper electrode prevents electron trapping and ghost phenomena in static radiography.

Segmenting the power supply line allows smooth insulation material application, resolving thickness defects caused by underlying electrode structures.

Plasma ashing removes photo-resist while depositing a protective silicon oxide layer on low-k dielectrics.

Liquid blocking rolls and air curtains prevent chemical treatment liquid from entering other process regions, ensuring uniform application.

A semiconductor memory device uses hierarchical bit lines to reduce side coupling capacitance.

Brazes a metallic optical separation grid to a wettable electrode face using self-alignment during soldering.

Phenanthrene compounds improve device lifetime and efficiency in blue organic light emitting diodes.

An auxiliary common line in an array substrate enables fringe field switching with a larger pixel electrode area.

An integrated damascene barrier film merges oxygen and hydrogen protection to reduce etch time and prevent misaligned metal contacts in FRAM fabrication.

Exposed auxiliary electrode sidewalls lower cathode resistance and voltage drop, ensuring uniform brightness across the display.

A 3D display panel uses stacked light emission units to emit orthogonal polarization light from primary and secondary pixels.

Adhesive layer openings overlap insulating layer apertures to secure electrodes and mitigate total internal reflection losses that trap light and generate heat.

A multilayered wiring structure uses separated conductive layers to maintain electrical connectivity across bending regions in flexible displays.

A selector material stack uses segmented barrier layers to limit diffusion between conductive and dielectric components.

Vertical shielding units block inclined light to stabilize the black reference level without enlarging the invalid area.

Vertical stacking of conductive layers through non-overlapping contact holes increases storage capacitor capacity without reducing the light emitting area.

Segmenting magnetic arrays with dedicated multiplexers reduces sense amplifier complexity while maintaining fast switching speeds.

Segmented mask openings form stepped sidewalls in array substrate metal films, preventing subsequent film layer slippage and ensuring complete coverage.

Oxide nanoparticles inhibit silver crystal growth during thermal processing, suppressing surface roughening and diffuse reflection for reliable light emission.

Radial thermal chokes segment the cooling plate to maintain thermal uniformity while minimizing thermal expansion issues.

Laser ablation removes surface impurities to enable robust weld formation while protecting delicate bond pads from mechanical damage.

High modulus backside layer prevents debris embedding into die attach film, eliminating electrical interference and costly processing steps.

Separate hole blocking regions block holes between overlapping light emitting areas to eliminate color mixing and improve manufacturing yield.

Subdividing chromaticity regions into smaller subregions allows selecting LEDs from different zones to improve color consistency and reduce LED waste.

Branching data lines connects pixel electrodes directly to gate lines, eliminating repair wiring that reduces aperture ratio and transmittance.

Protruding substrate columns equalize color filter heights, eliminating step differences that cause yellowish phenomena and degraded lateral visibility.

Segmented electrodes isolate uplink transmission from sensing paths, reducing noise interference for accurate coordinate calculation.

Conjugated ions dope graphene oxide to create a conductive hole injection layer, resolving conductivity loss from sp2 hybridization destruction.

Serially connected LED dies reduce leakage current and heat generation, enabling smaller heat dissipating devices.

Temperature-controlled gas inlet deposits organic layers onto substrates via a shielding element that thermally insulates the components.

Segmented semiconductor layers reduce dislocations to improve internal quantum efficiency in light emitting devices.

Segmenting the semiconductor layer into distinct films suppresses OFF current while maintaining low contact resistance for reliable ON current.

A hybrid MOS-PCM IC switch combines transistors with phase-change material cells to control signal transmissions.

An adjustable circular polarizer varies polarization efficiency to manage ambient light reflections in organic light-emitting diode displays.

A dielectric member separates adjacent inner lenses in a backside illumination pixel array to prevent light leakage between optical elements.

Multi-layer insulating films with specific thickness and dielectric ratios suppress source line electric field interference to improve display transmittance.

Segmented metal oxide layers with controlled oxygen deficiency stabilize variable resistance characteristics during reactive sputtering manufacturing.

A donor-acceptor luminogen exhibits aggregation-induced emission and intramolecular charge transfer to detect solvent, temperature, pressure, and electric field.

An Al—Ni—Cu precipitate on a second electrode layer minimizes contact resistance and prevents electrode damage during operation.

Dual infrared detecting portions measure internal pressure gradients to maintain vacuum integrity without additional sensors.

A dual-gate array substrate uses same-side gate lines and via-connected jumper wires to align pixel elements.

Through passages in a structured wafer allow etchant to remove the release layer, reducing etching time and preventing device adhesion during processing.

Nesting texture identifiers in via holes reduces substrate thickness and stress, preventing deformation while maintaining detection accuracy.