Magnetic Memory Emulating DRAM via Multiplexer Segmentation
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Solution Overview
Problem
Magnetic random access memory (MRAM) devices require more complex and larger sense amplifier circuitry to emulate dynamic random access memory (DRAM), leading to increased overhead and manufacturing costs.
Innovation Solution
A memory device structure comprising multiple magnetic memory arrays with a multiplexer and sense amplifier configuration that allows for efficient data bit reading and latching, enabling the emulation of DRAM with reduced complexity and footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional sense amplifier circuitry is used to emulate DRAM in MRAM devices, then DRAM functionality can be achieved, but device complexity and footprint increase significantly
Solution Approach 1:
The patent divides the memory system into multiple magnetic memory arrays, each with its own dedicated sense amplifier. This segmentation allows each sense amplifier to handle a specific array, reducing the complexity of individual sense amplifiers while maintaining overall DRAM emulation capability across the entire memory system.
Solution Approach 2:
The patent designs the sense amplifier circuitry to perform multiple functions: it can operate in both SRAM mode (for fast access) and DRAM mode (for high capacity), and can serve multiple memory arrays through the crossbar architecture. This multi-functionality reduces the need for separate dedicated circuits for different operating modes.
2Adaptability or versatility
If conventional sense amplifier circuitry is used to emulate DRAM in MRAM devices, then DRAM functionality can be achieved, but manufacturing costs increase
Solution Approach 1:
The patent merges the sense amplifier functionality with the memory array structure itself, where sense amplifiers are integrated directly into the crossbar architecture. This merging eliminates the need for separate, complex sense amplifier blocks, reducing manufacturing complexity and cost while maintaining DRAM emulation capability.
Solution Approach 2:
The sense amplifier circuitry is designed to serve multiple purposes across different memory arrays and operating modes, increasing utilization efficiency and reducing the total amount of circuitry needed, thereby lowering manufacturing costs.
3Area of stationary object
If multiple magnetic memory arrays are used to reduce overhead, then sense amplifier footprint is reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory system into multiple independent but identical memory arrays, each with simplified sense amplifier interfaces. This segmentation reduces the footprint of individual sense amplifiers while the modular nature of the segmentation keeps the overall system manageable and not excessively complex.
Solution Approach 2:
The patent uses a crossbar architecture that adds a spatial dimension to the memory organization, allowing multiple arrays to be accessed through row and column select lines. This dimensional approach efficiently manages multiple arrays without proportionally increasing control complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables the efficient emulation of DRAM functionality in MRAM devices, reducing manufacturing costs and complexity while maintaining the benefits of MRAM's fast switching speed and low power consumption.
Implementation Method 1
Upon application of an appropriate current or voltage to the magnetic memory element in the programming step, the electrical resistance of the magnetic memory element would change accordingly, thereby switching the stored logic in the respective memory cell
Implementation Method 2
When the magnetization directions of the magnetic free and reference layers are substantially parallel or oriented in a same direction, electrons polarized by the magnetic reference layer can tunnel through the insulating tunnel junction layer, thereby decreasing the electrical resistance of the MTJ
Data Source
AI summary
The present invention is directed to a magnetic memory device comprising a memory array structure that includes a first memory array comprising a first plurality of memory cells and a second memory array comprising a second plurality of memory cells. Each memory cell of the first and second plurality of magnetic memory cells includes a magnetic memory element and a two-terminal selector coupled in series. The memory array structure further includes a first multiplexer coupled to a third plurality of first conductive lines with each line connected to a respective column of the first plurality of memory cells; a second multiplexer coupled to a fourth plurality of first conductive lines with each line connected to a respective column of the second plurality of memory cells; a sense amplifier, whose input is connected to the output of the first multiplexer and the output of the second multiplexer; and one or more latches coupled to the sense amplifier.