Low-k Dielectric Patterning via Plasma Ashing
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Solution Overview
Problem
Low-k dielectric materials in semiconductor manufacturing are sensitive to plasma ashing, leading to damage and reduced critical dimension integrity as technology nodes advance, necessitating improved selectivity between organic masks and low-k dielectrics to minimize ashing damage and maintain dielectric constant consistency.
Innovation Solution
Incorporating both an oxygen radical source and a silicon source in the ashing plasma to remove organic masks while depositing a protective silicon oxide layer on low-k dielectric films, which can be subsequently removed with hydrofluoric acid, and using a high boiling point silicon source to form a reactive layer before plasma exposure to enhance patterning precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional plasma ashing is used to remove organic masks, then photo-resist removal is achieved, but low-k dielectric damage occurs and critical dimension integrity deteriorates
Solution Approach 1:
A silicon-containing protective layer is introduced as an intermediary between the plasma and the low-k dielectric. This layer absorbs the harmful plasma effects while allowing the photo-resist removal function to proceed, thereby protecting the low-k dielectric from damage during the ashing process
Solution Approach 2:
The plasma process is modified to deposit silicon oxide from silicon-containing precursors, converting the potentially harmful plasma exposure into a beneficial protective action. The same plasma that removes photo-resist also forms a protective silicon oxide layer on the low-k dielectric
2Ease of operation
If plasma ashing is applied to remove organic masks, then masking function is fulfilled, but critical dimension integrity is reduced
Solution Approach 1:
The silicon-containing protective layer is formed beforehand to cushion the low-k dielectric against the harsh plasma environment. This pre-formed layer acts as a buffer that prevents plasma-induced damage to the critical dimensions of the low-k dielectric structures
3Object-affected harmful factors
If silicon source is added to plasma to protect low-k dielectric, then ashing damage is reduced, but over-deposition may block photo-resist removal
Solution Approach 1:
The silicon source concentration and exposure time are carefully controlled to achieve partial deposition - enough to form a protective layer but not so much as to create an excessive barrier. This balanced approach ensures protection without compromising photo-resist removal efficiency
Solution Approach 2:
Process parameters such as silicon source concentration, plasma power, and exposure time are optimized to control the thickness of the silicon oxide layer. By adjusting these parameters, the protective layer thickness is maintained within a range that provides protection while allowing photo-resist removal to proceed effectively
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces low-k dielectric ashing damage, maintains critical dimension integrity, and prevents over-deposition that can block photo-resist removal, thereby enabling more precise patterning and consistent dielectric performance across advancing technology nodes.
Implementation Method 1
exposing the photo-resist layer to a plasma including an oxygen radical source and a silicon source to remove the photo-resist layer
Implementation Method 2
exposing the photo-resist layer to a plasma including an oxygen radical source and a silicon source
Implementation Method 3
soaking the low-k dielectric layer with a high boiling point silicon source
Data Source
AI summary
A significantly improved low-k dielectric patterning method is described herein using plasma comprising an oxygen radical source and a silicon source to remove the photo-resist layer.