Auxiliary Gate Antenna Diodes for Plasma Charge Discharge
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Solution Overview
Problem
In semiconductor manufacturing, the introduction of plasma treatments can lead to parasitic capacitance and leakage currents due to the accumulation of charge in sensitive areas, particularly in sophisticated SOI devices, which complicates design and increases manufacturing costs while potentially causing plasma-induced damage.
Innovation Solution
The implementation of auxiliary gate antenna diodes coupled with a discharge device to the semiconductor substrate, which helps in discharging unwanted charges during plasma treatments, thereby reducing parasitic capacitance and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If plasma treatments are applied to achieve highly directional etching and improved manufacturing precision, then etch directionality and manufacturing precision are improved, but charge accumulation in antenna structures occurs leading to parasitic voltages that may exceed breakdown voltage of gate dielectric
Solution Approach 1:
An auxiliary gate structure is introduced as an intermediary element between the plasma environment and the sensitive gate dielectric. This auxiliary gate acts as a mediator that can safely accumulate charge during plasma treatments, preventing charge buildup in the main gate electrode and avoiding breakdown of the gate dielectric layer.
Solution Approach 2:
The auxiliary gate structure is formed as a copy or replica of the main gate electrode structure, using similar materials and geometry. This copied structure serves the protective function of charge accumulation while maintaining compatibility with the plasma processing environment and the underlying device architecture.
2Reliability
If substrate diodes and conductive paths are added to provide discharge mechanisms for plasma-induced charge, then reliability against plasma damage is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The auxiliary gate structure is merged with the existing gate electrode structure, sharing the same formation process steps and materials. This integration allows the protective function to be achieved without adding separate discrete components, thereby reducing device complexity and manufacturing overhead.
Solution Approach 2:
The auxiliary gate structure serves multiple functions: it acts as a protective element during plasma processing by accumulating charge, and it can also function as a legitimate gate electrode for device operation. This multi-functionality eliminates the need for dedicated discharge structures that would otherwise be required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the impact of plasma-induced damage on sensitive device areas, improving device performance and simplifying design complexities by providing an efficient discharge mechanism for charge accumulation, thus minimizing adverse effects on semiconductor devices.
Implementation Method 1
a discharge device coupled to the base semiconductor layer and the auxiliary gate structure
Implementation Method 2
In a plasma technique, certain species in the plasma ambient may be ionized and appropriately accelerated to the substrate material to be treated
Implementation Method 3
certain species in the plasma ambient may be ionized and appropriately accelerated
Data Source
AI summary
One illustrative embodiment disclosed herein relates to a semiconductor device that includes, among other things, a semiconductor substrate including a base semiconductor layer, an active semiconductor layer, and a buried insulating layer positioned between the base semiconductor layer and the active semiconductor layer. The device further includes a set of functional gate structures including at least one functional gate structure formed above the active semiconductor layer, a first source/drain region positioned in the active semiconductor layer adjacent a first functional gate structure in the set, a first auxiliary gate structure positioned adjacent the first source/drain region, and a discharge device coupled to the base semiconductor layer and the first auxiliary gate structure.