Auxiliary Gate Lines Reduce Signal Delay in LCD Substrates
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Solution Overview
Problem
As display devices increase in size and resolution, the longer conductive lines in LCDs lead to increased resistance and signal delay, affecting gray scale display quality.
Innovation Solution
The implementation of an active-matrix substrate with auxiliary conductive lines and polarizing films formed from a same layer of transparent conductive material, connected via holes to reduce the resistance of gate and data lines, thereby minimizing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the display device size and resolution are increased, then the display quality is improved, but the resistance of gate lines and data lines increases
Solution Approach 1:
The patent divides the conductive lines into multiple segments by introducing auxiliary gate lines and auxiliary data lines that run parallel to the main lines. These auxiliary lines are connected at specific intervals through contact holes, effectively segmenting the long conductive paths into shorter sections. This segmentation reduces the overall resistance and capacitance of the conductive lines, thereby improving signal transmission quality in high-resolution displays.
Solution Approach 2:
The patent transitions from a two-dimensional layout to a three-dimensional structure by adding auxiliary conductive lines in the vertical dimension (different layers). The auxiliary gate lines and data lines are positioned on different layers and connected through contact holes, creating a multi-layer conductive network. This dimensional change allows for reduced line resistance without increasing the planar area, enabling high-resolution displays to maintain signal quality.
2Area of stationary object
If the conductive line length is increased to accommodate larger display sizes, then the display area is expanded, but the signal delay increases
Solution Approach 1:
By introducing auxiliary conductive lines connected at intervals, the patent segments the long conductive paths into shorter effective sections. This reduces the total resistance and capacitance along the signal path, thereby decreasing signal delay while maintaining the large display area.
Solution Approach 2:
The auxiliary conductive lines act as intermediaries that provide additional signal transmission paths. By distributing the signal through multiple parallel paths (main lines and auxiliary lines), the effective resistance is reduced, which decreases signal delay without requiring a reduction in display area.
3Reliability
If auxiliary conductive lines are added to reduce resistance, then the electrical performance is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of auxiliary conductive lines with the existing manufacturing processes for gate lines and data lines. The auxiliary lines are formed using the same deposition and patterning steps as the main conductive lines, and the contact holes connecting them are formed during the standard contact hole formation process. This merging approach minimizes additional process steps while achieving the electrical performance benefits.
Solution Approach 2:
The auxiliary conductive lines serve multiple functions: they reduce line resistance, provide additional signal paths, and can be integrated with the existing multi-layer structure for other display functions. This multi-functionality justifies the additional structural complexity by delivering multiple performance benefits simultaneously.
Data Source
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AI summary
The embodiments of the present invention provide a substrate and a manufacturing method thereof, as well as a display device. The substrate comprises: a base substrate, a plurality of gate lines arranged in parallel, a first insulating layer that covers the gate lines, a plurality of data lines located on the first insulating layer and perpendicular to the gate lines, a second insulating layer that covers the data lines, and pixel electrodes of sub-pixel areas enclosed by the data lines and the gate lines; polarizing films that cover the pixel electrodes; and first auxiliary gate lines arranged on the second insulating layer and parallel to the gate lines, at least two portions on each of the first auxiliary gate lines being electrically connected with at least two corresponding portions on the gate line through via holes that penetrate the first insulating layer and the second insulating layer, the first auxiliary gate lines and the polarizing films are formed by performing a same patterning process to a same layer of transparent conductive material. The embodiments of the present invention can reduce signal delay in a display device, and can be used for manufacture of a display.