Auxiliary Pattern Layout for Semiconductor Wafer Stress Balancing
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Solution Overview
Problem
Three-dimensional NAND memory devices experience warping of semiconductor wafers due to film stress from stacked metal films in memory cell regions, leading to deformation issues that affect manufacturing precision and yield.
Innovation Solution
Incorporating an auxiliary pattern with separation portions in the peripheral circuit arrangement region, intersecting with the word line direction at an angle greater than 45°, to balance film stress and prevent wafer deformation by distributing stress components evenly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If thin metal films are stacked in the memory cell arrangement region to increase storage density, then the storage capacity is improved, but the semiconductor wafer becomes warped due to film stress
Solution Approach 1:
The patent divides the peripheral circuit arrangement region into multiple segments by introducing auxiliary patterns with separation portions. These separation portions break up the continuous metal film structure into discrete segments, allowing the stress from each segment to be independently managed and distributed, thereby preventing overall wafer warping while maintaining the high-density storage structure in the memory cell region
Solution Approach 2:
The patent applies different structural configurations to different regions of the wafer. The memory cell arrangement region maintains its high-density stacked metal film structure for maximum storage capacity, while the peripheral circuit arrangement region incorporates auxiliary patterns with specific separation portions to locally manage stress. This localized structural differentiation allows each region to optimize its function without compromising the other
2Productivity
If the layout of thin metal films is optimized for storage density, then the manufacturing efficiency is improved, but the wafer warps in a specific direction affecting manufacturing precision
Solution Approach 1:
The patent introduces asymmetric auxiliary patterns in the peripheral circuit arrangement region, where the separation portions are strategically positioned to create an asymmetric distribution of metal films. This asymmetric layout is specifically designed to counterbalance the dominant stress direction caused by the memory cell region's metal film arrangement, thereby preventing directional wafer warping and maintaining manufacturing precision without reducing storage density
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a semiconductor substrate, which includes thereon a first region where memory elements are arranged and a second region where circuit elements driving the memory elements are arranged. The first region is provided with a stacked body including a plurality of metal films. Further, the stacked body is divided into a plurality of parts by first separation portions extending in a first direction. The second region is provided with an auxiliary pattern, which includes the stacked body together with a separation portion pair including a pair of second separation portions that divide the stacked body. The second separation portions extend in a second direction intersecting with the first direction.