Avalanche Photodiode Pixel Layout With Vertical High-Field Region

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

There is a limit to reducing pixel size in avalanche photodiode structures where the high field region is formed in the planar direction.

Innovation Solution

A light detecting element with pixels arranged in a matrix, featuring a first semiconductor layer of a specific conductivity type formed in the outer peripheral portion and a second semiconductor layer of opposite conductivity type on the inside, configuring the high field region to be formed in the depth direction of the substrate when a reverse bias voltage is applied.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the high field region is formed in the planar direction with a guard ring structure, then the photodiode achieves sufficient avalanche multiplication and edge breakdown protection, but the pixel size cannot be reduced further

Engineering Contradiction:
Improveedge breakdown protectionVSAvoidpixel size
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The patent transitions the high field region from planar (horizontal) formation to vertical (depth direction) formation by creating a vertically extending PN junction structure. The first semiconductor layer of first conductivity type and second semiconductor layer of second conductivity type are stacked vertically, causing the high field region to form in the depth direction rather than the planar direction, thereby enabling pixel size reduction while maintaining avalanche multiplication performance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent removes the guard ring structure entirely by forming the high field region vertically in the depth direction. The vertical PN junction structure inherently provides edge breakdown protection through its depth-direction field configuration, eliminating the need for separate guard ring components that occupy planar space

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If the high field region is formed in the planar direction, then the structure provides adequate avalanche multiplication, but the pixel area is constrained and cannot be reduced

Engineering Contradiction:
Improveavalanche multiplicationVSAvoidpixel area
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The patent reorients the high field region formation from the planar dimension to the depth dimension by creating a vertical PN junction. The first semiconductor layer and second semiconductor layer are arranged vertically, allowing the high field region to extend in the depth direction, which enables sufficient avalanche multiplication within a smaller planar pixel area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for a reduction in pixel size while maintaining sufficient high field regions, avoiding edge breakdown and improving jitter characteristics without the need for a guard ring.

Implementation Method 1

an avalanche photodiode (hereinafter referred to as an APO), which is a high-speed and high-sensitivity photodiode utilizing an electron avalanche that occurs when a reverse bias voltage is applied to a PN junction

Methodology Applied
Scientific EffectElectron avalanche: Electron Avalanche

Implementation Method 2

a light detecting element... pixels arranged in a form of a matrix... first semiconductor layer of a first conductivity type... second semiconductor layer of a second conductivity type

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS11791359B2Light detecting element and method of manufacturing same
Publication Date: 2023.10.17 SONY SEMICON SOLUTIONS CORP
  • US11791359B2 patent drawing
  • US11791359B2 patent drawing
  • US11791359B2 patent drawing

AI summary

The present technology relates to a light detecting element and a method of manufacturing the same that make it possible to reduce pixel size. The light detecting element includes a plurality of pixels arranged in the form of a matrix. Each of the pixels includes a first semiconductor layer of a first conductivity type formed in an outer peripheral portion in the vicinity of a pixel boundary, and a second semiconductor layer of a second conductivity type opposite from the first conductivity type formed on the inside of the first semiconductor layer as viewed in plan. A high field region formed by the first semiconductor layer and the second semiconductor layer when a reverse bias voltage is applied is configured to be formed in a depth direction of a substrate. The present technology is, for example, applicable to a photon counter or the like.