Avalanche-Protected Transistors Using Bottom Breakdown Current Path
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Solution Overview
Problem
Semiconductor devices face performance degradation due to parasitic inductance-induced voltage spikes and avalanche breakdowns, leading to reduced on-current and potential functional failures during high voltage and high current switching conditions.
Innovation Solution
The implementation of a buried doped well within a field effect transistor that induces breakdown at the bottom of the drain region instead of the sidewall, forming a Zener diode-like structure to manage avalanche breakdowns by directing impact ionization charges through a bottom breakdown path, thereby enhancing single pulse and repetitive avalanche energy absorption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional field effect transistor structure is used, then the device can operate under normal switching conditions, but the device suffers performance degradation and potential functional failures during avalanche breakdowns caused by parasitic inductance-induced voltage spikes
Solution Approach 1:
The patent segments the breakdown path by introducing a buried first-conductivity-type well that creates a dedicated bottom breakdown current path, separating the avalanche breakdown location from the gate dielectric. This segmentation directs impact ionization charges away from sensitive components, preventing damage while maintaining device operation during UIS events.
Solution Approach 2:
The buried first-conductivity-type well acts as an intermediary structure that mediates the avalanche breakdown process. It provides a controlled path for charge carriers during breakdown, intercepting impact ionization charges before they can reach and damage the gate dielectric, thus protecting the device during high-stress conditions.
2Reliability
If the breakdown occurs at the sidewall of the drain region, then the conventional structure is maintained, but the gate dielectric is exposed to impact ionization charges causing performance degradation
Solution Approach 1:
The patent moves the breakdown location from the lateral sidewall dimension to the vertical bottom dimension by introducing a buried well. This dimensional shift redirects the breakdown current path vertically through the buried well to a safe location away from the gate dielectric, protecting it from impact ionization charges while maintaining a relatively simple structure.
3Reliability
If the device is designed for high single pulse avalanche energy (EAS) and high repetitive avalanche energy (EAR), then the device can withstand UIS events, but the structure requires additional components like a buried doped well
Solution Approach 1:
The buried first-conductivity-type well serves multiple functions: it provides a breakdown protection path during avalanche events, acts as a charge collection region, and influences the electric field distribution to enhance breakdown characteristics. This multi-functionality allows the device to achieve high EAS and EAR ratings without requiring separate protective structures for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves the semiconductor device's reliability and minimizes performance degradation under high voltage and high current conditions by redirecting impact ionization charges away from the gate dielectric, reducing the risk of permanent damage and maintaining circuit performance.
Implementation Method 1
Devices may enter into an avalanche mode during switching cycles, and may suffer from performance degradation caused by damage that avalanches of electrical charges cause at the structural level
Implementation Method 2
inducing breakdown at the bottom of the drain region instead of the sidewall, forming a Zener diode-like structure to manage avalanche breakdowns by directing impact ionization charges through a bottom breakdown path
Data Source
AI summary
An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.