Back-Biased MOSFET Amplifier for Low-Noise Capacitive Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing amplifiers for capacitive sensors face challenges in reducing noise and impedance while operating within low power constraints, particularly in applications where common-mode voltage is minimal or absent.
Innovation Solution
The amplifier design includes a bias circuit, an open-loop gain stage with specific MOSFET configurations, and a buffer stage with a super source follower, which collectively provide low-impedance output while minimizing current draw and compensating for zero common-mode voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional amplifier designs are used for capacitive sensors, then the amplifier can provide sufficient gain and buffering, but the noise level increases and impedance remains high
Solution Approach 1:
The patent changes the operating parameters of the MOSFETs by applying back-bias voltages to the bulk connections of the PMOS transistors. This parameter change modifies the threshold voltages and operating points of the transistors, enabling the amplifier to achieve lower noise performance and reduced output impedance while maintaining sufficient gain for capacitive sensor signals
2Object-affected harmful factors
If higher power is consumed to reduce noise and impedance, then signal quality improves, but power consumption exceeds the 30 micro-amps constraint
Solution Approach 1:
The patent achieves low noise and low impedance performance at ultra-low power by carefully selecting and adjusting operating parameters such as bias voltages, transistor dimensions, and back-bias levels. These parameter optimizations enable the amplifier to deliver enhanced signal quality while consuming less than 30 micro-amps of current
Solution Approach 2:
The patent replaces conventional amplifier architectures with a specialized MOSFET-based design featuring back-biased PMOS transistors. This substitution creates a novel circuit mechanism that achieves low noise and low impedance through electrostatic control of the bulk terminals, rather than through traditional high-power biasing schemes
3Adaptability or versatility
If the amplifier is designed for zero common-mode voltage, then compatibility with capacitive sensors improves, but the circuit becomes more complex
Solution Approach 1:
The patent employs asymmetric circuit configuration where the PMOS transistors have their bulk connections independently biased, creating an unbalanced structure that is specifically optimized for zero common-mode voltage operation. This asymmetric design provides superior compatibility with capacitive sensors while the complexity is managed through systematic bias circuit design
Data Source
AI summary
In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.