Amplififers With Field-Effect Devices TRIZ Cases

Negative capacitance and adaptive biasing help an LDO reject supply noise across process corners while avoiding unnecessary power draw.

A PMOS-NMOS output stage uses parallel gate capacitor and impedance biasing to keep linearity and power efficiency under low headroom.

A MOS-capacitor gate circuit cancels parasitic coupling in LDO regulators to improve PSR across process corners and avoid unnecessary bias power.

Gate line extensions overlapping substrate indentations cut gate resistance and gate-to-body capacitance, improving LNA gain and oscillation frequency.

Calibration logic switches parallel cascode branches to tune transmitter output resistance, improving impedance matching and reducing reflections.

Passive butterfly networks perform analog FFT operations from the input signal itself, avoiding active devices, clocks, and standby power.

A resistor-free current-feedback instrumentation amplifier cuts front-end noise and current draw for stable monolithic MEMS and NEMS sensor readout.

Multiple LNAs with frequency-based selection improve band isolation, linearity, and noise figure in intraband and interband carrier aggregation.

Back-biased PMOS stages and a super source follower cut noise and output impedance for capacitive sensors while staying under 30 micro-amps.

Reference voltages tied to input or output common-mode levels stabilize transistor source-gate bias, improving dynamic amplifier swing and stability.

Alternating capacitors and switch-controlled gain let a dynamic amplifier extend output swing and flexibility despite lower CMOS threshold voltage.

An inductance network at the transistor source compensates output capacitance to raise pole frequency, widen bandwidth, and cut power use.

A cascode sensor circuit reuses bias current for amplification, cutting power and area while delivering linear, low-noise readout.

Bias control switches current sources off during transients and on in steady state, balancing high slew rate with high amplifier gain.

An inductance network at the transistor source compensates output capacitance to raise non-dominant pole frequency with lower power.

Precharging the compensation capacitor off-output stabilizes slew rate and cuts peak-current EMI in operational amplifier circuits.

A t-coil, capacitor splitting, and inductance tree amplifier extends transceiver bandwidth 4-5x while keeping sub-ps jitter above 45 Gb/s.

A long-gate pHEMT active load paired with an HBT raises differential amplifier gain while cutting chip area, current use, and noise.

A feedback sensing circuit boosts linear gain for tiny PN junction forward-voltage changes, improving temperature control of power transistors.

A three-stage current-summing circuit decouples DC slope generation from supply voltage, enabling tunable gradient and intercept.

A movable current injection point on the feedback resistor enables variable RF gain while holding input impedance, noise, and power in check.

Using FET feedback with bipolar input transistors, this case shows low-noise amplification at low current, low voltage, and high CMOS integration.

Cascaded two-stage voltage regulator stabilizes output using a capacitor-less PMOS source follower and operational amplifier feedback loop.

Three-stage circuit architecture generates tunable DC slope via voltage independent current, overcoming fixed gradient limits of resistor dividers.

An operational amplifier drives transistor gates to maintain determinate node voltages in a current mirror circuit.

Dual-region field effect transistors and a voltage modulator cancel transconductance changes, reducing harmonic distortion in RF amplifiers.

A gallium nitride field-effect transistor uses a voltage dividing circuit to maintain equal potential across its field plate electrode.

A solid-state imaging device uses a dedicated correction unit to compensate for amplifier offset voltage.

A JFET-based overvoltage protection circuit uses a selector to control clamp transistor resistance for symmetrical current limiting.