LDO Pass-Transistor Gate Circuit for PSR Noise Cancellation
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Solution Overview
Problem
Low dropout (LDO) regulators face challenges in enhancing power supply rejection (PSR) due to parasitic capacitances that couple supply noise to the output, leading to degraded PSR performance across process corners and inefficient power usage when high PSR is not required.
Innovation Solution
A system and method that utilize a metal-oxide-semiconductor (MOS) capacitor to generate negative capacitance, which is coupled to the gate of the pass transistor, effectively canceling parasitic capacitances and enhancing PSR performance, while also incorporating adaptive current biasing and a high-pass filter to optimize power efficiency by enabling/disabling the PSR enhancer based on the circuit's needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional LDO regulator is used, then the circuit receives regulated voltage, but power supply noise couples to the output through parasitic capacitances, degrading PSR performance
Solution Approach 1:
The patent converts the harmful parasitic capacitances into a beneficial effect by generating a negative capacitance that exactly cancels them. The MOS capacitor and amplifying circuit create a negative capacitance equal in magnitude but opposite in sign to the parasitic capacitances, transforming the noise-coupling problem into a solution that actively rejects power supply noise and enhances PSR performance.
Solution Approach 2:
The patent introduces an intermediary negative capacitance circuit between the power supply noise source and the LDO regulator output. This intermediate negative capacitance acts as a mediator that counteracts the direct coupling path through parasitic capacitances, effectively blocking noise transmission while maintaining regulated voltage output.
2Reliability
If PSR enhancement circuitry is always enabled, then PSR performance is improved across all conditions, but power consumption increases when high PSR is not required
Solution Approach 1:
The patent implements dynamic control of the PSR enhancement circuitry by enabling or disabling the negative capacitance generation based on operational conditions. The circuit can be activated when high PSR is needed (e.g., during noisy power supply conditions) and deactivated when standard regulation suffices, allowing the system to adapt its power consumption to actual performance requirements.
Solution Approach 2:
The patent changes the operational state of the PSR enhancement circuitry by switching between enabled and disabled modes. This parameter change allows the system to optimize the trade-off between PSR performance and power consumption, activating the enhancement only when necessary rather than maintaining it continuously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves PSR performance across process corners and enhances power efficiency by accurately canceling capacitive coupling effects and dynamically adjusting bias current based on the current load, ensuring high PSR only when necessary.
Implementation Method 1
A first aspect relates to a system including an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.
Implementation Method 2
A second aspect relates to a method for enhancing power supply rejection for a low dropout (LDO) regulator. The method includes generating a negative capacitance using a metal-oxide-semiconductor (MOS) capacitor, and coupling the negative capacitance to a gate of a pass transistor of the LDO regulator.
Data Source
AI summary
In certain aspects, a system includes an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.