Low-Noise Amplifier Feedback Circuit for Low-Current CMOS Integration
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Solution Overview
Problem
Existing amplifier circuits face challenges with high integration in larger components, high supply voltage requirements, and high power dissipation, making them unsuitable for low noise amplification with low current consumption.
Innovation Solution
The amplifier circuit is redesigned with FETs in the feedback stage and a specific connection of transistors to reduce voltage and current consumption, allowing for integration in CMOS technology and low noise amplification, using FETs and bipolar transistors in a CMOS circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If bipolar transistors are used in the amplifier circuit, then low noise amplification is achieved, but integration difficulty increases and production costs rise
Solution Approach 1:
The patent combines bipolar transistors (for low noise performance) with CMOS technology (for easy integration) by implementing a differential amplifier circuit where the input stage uses bipolar transistors Q1 and Q2, while the rest of the circuit including transistors Q3-Q8 and resistors R1-R4 is implemented in CMOS technology. This merging allows the circuit to achieve low noise amplification while maintaining compatibility with standard CMOS fabrication processes, thus resolving the contradiction between noise performance and integration ease
2Reliability
If high supply voltage is used, then amplifier performance is improved, but power consumption increases
Solution Approach 1:
The patent employs parameter changes by implementing a feedback mechanism that dynamically adjusts the operating point of the amplifier. The feedback network consisting of resistors R1-R4 and transistors Q3-Q8 monitors the output and adjusts the bias conditions to maintain optimal performance at lower supply voltages. This allows the amplifier to achieve reliable performance without requiring high supply voltages, thus reducing power consumption while maintaining amplifier reliability
3Power
If high current is used, then amplification capability is improved, but power dissipation increases
Solution Approach 1:
The patent implements dynamic current management through the feedback stage involving transistors Q3-Q8 and resistors R1-R4. This feedback mechanism dynamically adjusts the current distribution in the amplifier circuit based on the signal conditions, ensuring that sufficient current flows through the input bipolar transistors for adequate amplification capability, while simultaneously reducing unnecessary current consumption in other parts of the circuit. This dynamic adjustment resolves the contradiction between amplification capability and power dissipation by optimizing current usage in real-time
Data Source
AI summary
The invention relates to an amplifier circuit comprising supply terminals (12, 14) for supplying the circuit with first and second supply potentials (Vdd, Vss); a current path, which runs from the first supply terminal (12) via a first biased transistor (P1a, P1b), a first node (K1a, K1b), an input transistor (Q1a, Q1b), a second node (K2a, K2b) and a second biased transistor (N1a, N1b) to the second supply terminal (14), wherein a control terminal of the input transistor is loaded with an input signal (inp-inn), and wherein the second node (K2a, K2a) forms a pick-up in a resistor chain (R2a, R1, R2b), at whose ends is supplied an output signal (outp-outn) as a voltage drop; and a feedback stage enabling the current to flow the resistor chain (R2a, R1, R2b) dependent on the input signal (inp-inn) so that the current flowing through the input transistor (Q1a, Q1b) is essentially independent of the input signal (inp-inn), wherein the feedback stage has a pair of complementarily coupled transistors (P3a, N3a, P3b, N3b) with an intervening current output node (K3a, K3b). To increase the scope of application of such an amplifier and achieve a low noise amplification at a low current consumption, provision is made, according to the invention, for the complementarily coupled transistors (P3a, N3a, P3b, N3b) to be designed as FETs and the first node (K1a, K1b) to be connected on the one hand via a third biased transistor (N2a, N2b) to the second supply terminal (14) and on the other hand to a gate terminal of one (N3a, N3b) of the complementarily coupled transistors (P3a, N3a, P3b, N3b).