Pseudo Class-AB Output Circuit for Linearity and Low Headroom
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Solution Overview
Problem
High drive current applications face challenges in achieving both linearity and power efficiency, with class-A structures offering poor power efficiency, class-B structures having poor linearity, and class-AB structures suffering from insufficient headroom.
Innovation Solution
A pseudo class-AB circuit design incorporating a first PMOS and NMOS with a capacitor and impedance component in parallel between their gate terminals, along with a bias circuit that generates bias currents to mirror impedance components, ensuring proper biasing and maintaining high transconductance even at low frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a class-A structure is used, then linearity is improved, but power efficiency deteriorates
Solution Approach 1:
The circuit dynamically switches between class-A and class-AB operation modes based on signal conditions. The first and second capacitors create different operating regions: at low frequencies the capacitors are effectively open circuits enabling class-A operation for superior linearity, while at high frequencies they enable class-AB operation for improved power efficiency. This dynamic mode switching resolves the contradiction by adapting the operating class to the specific application requirements.
2Use of energy by moving object
If a class-B structure is used, then power efficiency is improved, but linearity deteriorates
Solution Approach 1:
The circuit dynamically switches between class-AB and class-A operation modes based on signal conditions. The first and second capacitors create different operating regions: at low frequencies the capacitors are effectively open circuits enabling class-A operation for superior linearity, while at high frequencies they enable class-AB operation for improved power efficiency. This dynamic mode switching resolves the contradiction by adapting the operating class to the specific application requirements.
3Use of energy by moving object
If a class-AB structure is used, then both linearity and power efficiency are improved, but headroom deteriorates
Solution Approach 1:
The circuit dynamically switches between class-A and class-AB operation modes based on signal conditions. The first and second capacitors create different operating regions: at low frequencies the capacitors are effectively open circuits enabling class-A operation for superior linearity, while at high frequencies they enable class-AB operation for improved power efficiency. This dynamic mode switching resolves the contradiction by adapting the operating class to the specific application requirements.
4Power
If high drive current is used, then output capability is improved, but power consumption increases
Solution Approach 1:
The circuit dynamically switches between class-A and class-AB operation modes based on signal conditions. The first and second capacitors create different operating regions: at low frequencies the capacitors are effectively open circuits enabling class-A operation for superior linearity, while at high frequencies they enable class-AB operation for improved power efficiency. This dynamic mode switching resolves the contradiction by adapting the operating class to the specific application requirements.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A circuit (100) with a pseudo class-AB structure is shown. The circuit (100) has an output stage, a first capacitor (C1), and a first impedance component (R1). The output stage has a first PMOS (p-type Metal-Oxide-Semiconductor Field-Effect Transistor) and a first NMOS (n-type MOSFET). The first connection node (n1) between the drain terminal of the first PMOS (MP1) and the drain terminal of the first NMOS (MN1) is coupled to the first output terminal (VOP) of the circuit (100). The first capacitor (C1) is coupled between the gate terminal of the first PMOS (MP1) and the gate terminal of the first NMOS (MN1). The first impedance component (R1) is coupled in parallel with the first capacitor (C1) between the gate terminal of the first PMOS (MP1) and the gate terminal of the first NMOS (MN1).