Back Gate Biasing for Dense CMOS Integration
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Solution Overview
Problem
Conventional semiconductor transistor devices using silicon on insulator (SOI) technology face limitations in achieving dense CMOS circuit layouts due to the need for separate electrical contacts to n-type and p-type back gates, which restricts circuit density and integration of SRAM and logic functions on the same substrate.
Innovation Solution
The method involves using doped substrate regions with different doping types as back gates, biased to a common potential, forming a diode junction with a functional region, allowing for dense CMOS circuit fabrication with a single common substrate bias contact, enabling dual-Vt transistors and complementary MOS logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate electrical contacts are provided for n-type and p-type back gates, then proper biasing of back gates is achieved, but circuit density is reduced and integration of SRAM and logic functions is restricted
Solution Approach 1:
The patent merges separate back gate contacts into a single common substrate contact that provides biasing for both n-type and p-type back gates. The substrate itself is doped to function as the back gate, eliminating the need for separate contacts and enabling higher circuit density while maintaining proper biasing control.
Solution Approach 2:
The single common substrate contact serves multiple functions: it provides the back gate bias for both n-type and p-type transistors, acts as a substrate contact, and enables the substrate to function as the back gate dielectric. This multi-functional approach reduces the number of required contacts and improves integration.
2Adaptability or versatility
If doped substrate regions are used as back gates with different doping types, then dual-Vt transistors are enabled, but device complexity increases
Solution Approach 1:
The patent applies local quality by creating selectively doped regions within the substrate. n-type doped regions serve as back gates for p-type transistors while p-type doped regions serve as back gates for n-type transistors. This localized doping approach enables dual-Vt transistor operation without requiring complex external biasing circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances circuit density by eliminating the need for separate back gate contacts, allowing for the integration of SRAM and logic functions on the same substrate with improved threshold voltage control and reduced variability, facilitating the construction of high-density arrays of SRAM devices and logic circuitry.
Implementation Method 1
implanting through the semiconductor layer and the insulating layer a functional region to be adjacent to the top surface of the substrate, the functional region having a first type of conductivity; implanting through the semiconductor layer and the insulating layer a back gate region
Implementation Method 2
The implanted back gate region is not connected to an electrical contact so that during operation it is biased by leakage and capacitive coupling to the same potential as a functional region of the substrate in which it is implanted and with which it forms a diode junction
Data Source
AI summary
A method to fabricate a structure includes providing a silicon-on-insulator wafer, implanting through a semiconductor layer and an insulating layer a functional region having a first type of conductivity to be adjacent to a top surface of the substrate; implanting within the functional region through the semiconductor layer and the insulating layer an electrically floating back gate region having a second type of conductivity; forming isolation regions in the semiconductor layer; forming first and second transistor devices to have the same type of conductivity over the semiconductor layer such that one of the transistor devices overlies the implanted back gate region and the other one of the transistor devices overlies only the underlying top surface of the functional region not overlapped by the implanted back gate region; and providing an electrical contact to the functional region for applying a bias voltage.