Back Gate Impurity Doping for SOI CMOS Threshold Voltage Control
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Solution Overview
Problem
The complexity of process and structure in threshold voltage adjustment for semiconductor integrated circuit devices, particularly in bulk and SOI hybrid CMIS devices, and single-type CMIS devices with N-channel and P-channel MISFETs, necessitates a simplification of the gate stack structure.
Innovation Solution
Introducing impurities into the back gate semiconductor regions of SOI semiconductor CMISFET integrated circuit devices with high-k gate insulating films and metal gate electrodes to adjust the threshold voltage, simplifying the gate stack structure by using lanthanum-doped or aluminum-doped high-k gate insulating films and metal gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple kinds of gate stacks are used to optimize threshold voltage control in bulk and SOI hybrid CMIS devices, then threshold voltage control is improved, but process and structure complexity increases
Solution Approach 1:
The patent applies local quality by introducing impurities specifically into the back gate semiconductor region to adjust threshold voltage locally, rather than requiring different gate stack structures for different threshold voltage requirements. This allows different threshold voltages to be achieved through localized impurity doping in the back gate region while maintaining a uniform gate stack structure across the device.
Solution Approach 2:
The patent changes physical parameters by controlling the concentration and type of impurities introduced into the back gate semiconductor region. By varying impurity concentration, the threshold voltage can be adjusted without changing the gate stack structure, thus resolving the contradiction between threshold voltage control precision and structural complexity.
2Device complexity
If impurity introduction method is used to adjust threshold voltage, then gate stack structure is simplified, but threshold voltage adjustment precision may be affected
Solution Approach 1:
The patent precisely controls threshold voltage adjustment by varying impurity concentration parameters in the back gate region. The method uses controlled impurity introduction with specific concentration ranges to achieve desired threshold voltages, maintaining precision while simplifying the gate stack structure.
Solution Approach 2:
The patent replaces complex mechanical/structural modifications of the gate stack with a chemical/doping-based approach. Instead of changing physical gate stack configurations, the method uses impurity diffusion and electrical field effects in the back gate region to achieve threshold voltage control, simplifying the overall structure while maintaining adjustment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reliable threshold voltage adjustment, simplifying the gate stack structure and reducing the complexity of the manufacturing process, thereby enhancing the reliability and efficiency of the semiconductor integrated circuit devices.
Implementation Method 1
a first gate insulating film having a high-k insulating film and a first gate electrode film having a metal layer
Implementation Method 2
a first gate electrode film having a metal layer
Data Source
AI summary
A bulk & SOI hybrid CMIS device, in which an I/O bulk part and a core logic SOI part are mounted, needs a number of gate stacks to optimize threshold voltage control and causes a problem that the process and structure become complicated. The present invention adjusts the threshold voltage of MISFET at the corresponding part by introducing impurities into any of back gate semiconductor regions, in an SOI semiconductor CMISFET integrated circuit device having a high-k gate insulating film and a metal gate electrode.