Back Gate Draw-Out Region for Parasitic Transistor Suppression
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing device size due to mask misalignment and increased resistance values in the deep portion of the back gate region, which complicates the suppression of parasitic transistor operation and modulation of the MOSFET threshold.
Innovation Solution
The semiconductor device incorporates a back gate draw-out region formed deeper than the source region, across the entire opening of the contact hole, reducing resistance values and allowing for a miniaturized contact hole shape, achieved through ion implantation under specific conditions using the insulating layer as a mask and utilizing the contact hole for forming the back gate draw-out region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the contact hole width is increased to account for mask misalignment, then manufacturing precision is improved, but device size increases
Solution Approach 1:
The back gate draw-out region is formed in advance before the contact hole is formed. By pre-forming this region that extends deeper than the source region and positioning it to correspond with the contact hole location, the patent eliminates the need to increase contact hole width for mask misalignment compensation. The preliminary formation of the draw-out region ensures that even if mask misalignment occurs during contact hole formation, the back gate region remains effectively connected.
2Ease of manufacture
If the P type diffusion layer is formed by thermal diffusion, then ease of manufacture is improved, but resistance value in deep portion increases
Solution Approach 1:
The patent extends the back gate region in the depth dimension by forming the back gate draw-out region deeper than the source region. This dimensional extension allows the back gate region to reach lower resistance zones in the semiconductor substrate, thereby reducing the overall resistance value of the back gate region while maintaining the simplicity of thermal diffusion processing.
3Reliability
If the P type diffusion layer is formed across a large area in the deep portion of the back gate region, then resistance value is reduced, but device size increases
Solution Approach 1:
The back gate draw-out region is formed with localized high-quality P type doping in the deep portion of the back gate region, specifically where it corresponds to the contact hole location. This localized doping approach reduces resistance in the critical deep region without requiring extensive lateral expansion of the P type diffusion layer, thereby maintaining compact device dimensions.
4Ease of manufacture
If the P type diffusion layer is formed by thermal diffusion, then ease of manufacture is improved, but formation region in deep portion is reduced
Solution Approach 1:
The back gate draw-out region is formed by thermal diffusion in advance, creating a preliminary P type diffusion layer that extends deeper than the source region. This preliminary formation establishes a foundation that reduces resistance in the deep portion and prepares the structure for subsequent contact hole formation, allowing the simple thermal diffusion process to achieve deeper penetration than would be possible without this pre-formed structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses parasitic transistor operation, reduces device size, and minimizes contact resistance, enabling more precise control over the MOSFET threshold without the need to account for mask misalignment during manufacturing.
Implementation Method 1
a back gate draw-out region is formed in the back gate region, and the back gate draw-out region is formed in a portion deeper than the source region
Data Source
AI summary
In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the present invention, for example, a MOS transistor, a P type diffusion layer 5 as the back gate region, and an N type diffusion layer 8 as a drain region, are formed in an N type epitaxial layer 4. In the P type diffusion layer 5, an N type diffusion layer 7 as a source region and a P type diffusion layer 6 are formed. The P type diffusion layer 6 is formed by performing ion implantation twice so as to correspond to a shape of a contact hole 15. Moreover, impurity concentrations in surface and deep portions of the P type diffusion layer 6 are controlled. By use of this structure, a device size is reduced, and an operation of a parasitic NPN transistor is suppressed.