Back Gate Isolation Regions for MOSFET Short Channel Effects
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Solution Overview
Problem
The scaling down of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) leads to short channel effects and challenges in maintaining electrical isolation between back gates of adjacent MOSFET devices, which complicates the adjustment of threshold voltage and increases device resistance.
Innovation Solution
A semiconductor device with a back gate isolation region is developed, where PNPN or NPNP junctions are formed between the back gates and isolation regions, and shallow trench isolations are used to electrically isolate adjacent MOSFETs, allowing for different doping polarities and bias electrical fields in back gates and isolation regions, thereby enhancing electrical isolation and reducing device resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET size is scaled down to improve integration level, then integration density increases, but short channel effects worsen and threshold voltage control becomes difficult
Solution Approach 1:
The gate control function is segmented into front gate (for main switching) and back gate (for threshold voltage control and short channel effect suppression). The back gate's doping regions extend into the semiconductor substrate, providing enhanced electrostatic control over the channel, which effectively suppresses short channel effects even in scaled-down devices.
Solution Approach 2:
The invention adds a vertical dimension to gate control by introducing the back gate beneath the insulating buried layer. This vertical stacking configuration allows the back gate to exert control over the channel from below, providing additional electrostatic control that compensates for the reduced channel length in scaled devices.
2Adaptability or versatility
If back gates are disposed under insulating buried layer for each MOSFET to adjust threshold voltage individually, then threshold voltage adjustment capability improves, but electrical isolation between adjacent back gates becomes difficult to ensure
Solution Approach 1:
Shallow trench isolation structures serve as intermediary elements between adjacent back gates. These isolation trenches, filled with insulating material, physically separate the doped regions of adjacent MOSFETs in the semiconductor substrate, preventing electrical leakage and crosstalk while allowing each back gate to independently control its associated threshold voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively isolates back gate conductive paths of adjacent MOSFETs, reducing the risk of accidental breakdown and allowing for a simpler process flow and cost savings by potentially using fewer back gate conductive paths.
Implementation Method 1
back gate conductive paths of adjacent MOSFETs are electrically isolated from each other by means of PNPN junctions or NPNP junctions formed by the back gates and the back gate isolation regions
Implementation Method 2
a shallow trench isolation, wherein the shallow trench isolation is formed between adjacent MOSFETs to isolate the adjacent MOSFETs from each other
Data Source
AI summary
The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, an insulating buried layer, and a semiconductor layer, wherein the insulating buried layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the insulating buried layer; adjacent MOSFETs formed in the SOI wafer, wherein each of the adjacent MOSFETs comprises a back gate formed in the semiconductor substrate and a back gate isolation region formed completely under the back gate; and a shallow trench isolation, wherein the shallow trench isolation is formed between the adjacent MOSFETs to isolate the adjacent MOSFETs from each other, wherein a PN junction is formed between the back gate and the back gate isolation region of each of the adjacent MOSFETs. According to embodiments of the present disclosure, a PN junction is formed between the back gate isolation regions of the adjacent MOSFETs. In addition to back gate isolation implemented by the shallow trench isolation between the adjacent MOSFETs, the adjacent MOSFETs are also isolated by means of PNPN junctions or NPNP junctions formed in the back gates and the back gate isolation regions. As a result, the semiconductor device has a better isolation effect, and thus the possibility of accidental breakdown of the semiconductor device is substantially reduced.