Back-Gate Data Latch Circuit for High-Margin NAND Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current data latch circuits in NAND memory systems face challenges in reducing circuit area while maintaining high transfer margins and rates, leading to increased power consumption and complexity.
Innovation Solution
The proposed data latch circuit configuration includes PMOS transistors with distinct power supply voltages applied to their back gates and sources, allowing for reduced circuit area by optimizing transistor configurations and power management, specifically using depletion NMOS transistors to generate higher voltage supplies for back gates during data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional data latch circuit configurations are used, then circuit area is reduced, but transfer margin and transfer rate decrease
Solution Approach 1:
The data latch circuit is segmented into multiple transistor stages with distinct functionality. The circuit uses a first transistor (input side) and a second transistor (output side) with different conductivity types, allowing each segment to be optimized for its specific function while contributing to overall high transfer margin without proportionally increasing area
Solution Approach 2:
Different regions of the circuit are assigned different conductivity types and voltage characteristics. The first transistor has first conductivity type optimized for input coupling, while the second transistor has second conductivity type optimized for output drive, allowing local optimization of transfer characteristics without uniform area expansion
2Use of energy by stationary object
If conventional data latch circuit configurations are used, then circuit area is reduced, but power consumption increases
Solution Approach 1:
The circuit employs dynamic voltage control where different voltage levels (first voltage and second voltage) are applied to different transistors based on operational requirements. This dynamic voltage management allows power consumption to be optimized without requiring larger circuit area for voltage regulation components
Solution Approach 2:
The invention changes the voltage parameter distribution across the circuit by applying distinct first and second voltages to different transistor gates and sources. This parameter optimization enables reduced power consumption while maintaining compact circuit area through efficient voltage utilization
3Productivity
If conventional data latch circuit configurations are used, then circuit complexity is reduced, but transfer rate decreases
Solution Approach 1:
The circuit merges the input coupling function and output drive function into a unified two-transistor configuration where the first and second transistors work together in series. This merging achieves high transfer rate through coordinated operation while avoiding the complexity of separate dedicated circuits for each function
Solution Approach 2:
The two-transistor configuration serves multiple functions simultaneously: the first transistor provides input signal coupling, the second transistor provides output signal drive, and together they enable bidirectional data transfer with high speed. This multi-functionality achieves high transfer rate without proportional increase in circuit complexity
Data Source
AI summary
A data latch circuit according to embodiments described herein includes a first circuit and a second circuit. The first circuit has a first transistor with a first conductivity type and a second transistor with a second conductivity type that differs from the first conductivity type being connected in series and stores a first logical value. The second circuit has a third transistor with the first conductivity type and a fourth transistor with the second conductivity type being connected in series and stores a second logical value being an inversion of the first logical value. The data latch circuit enables one of a first voltage and a second voltage that differs from the first voltage to be applied to back gates of the first transistor and the third transistor and enables a third voltage to be applied to sources of the first transistor and the third transistor.