Back-Junction Solar Cell Sea-Island Layer Layout for Carrier Lifetime
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Solution Overview
Problem
Back-junction solar cells face performance limitations due to exposure of the semiconductor substrate during patterning, which affects carrier lifetime and efficiency.
Innovation Solution
The method involves forming a first semiconductor layer in a sea or island shape in the second region of the semiconductor substrate, suppressing exposure during patterning, and ensuring the first semiconductor layer remains between the substrate and the second semiconductor layer, thereby improving carrier collection and solar cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the first semiconductor layer is completely removed in the second region during patterning, then the manufacturing process is simplified, but the back surface of the semiconductor substrate is exposed causing carrier lifetime degradation
Solution Approach 1:
The patent introduces a resist layer as an intermediary mask during the patterning process. The resist layer is formed on the first semiconductor layer in the second region, and then selectively removed to create openings that define the final pattern. This intermediary resist layer enables precise control over which areas of the first semiconductor layer are removed, preventing complete removal in the second region and thus avoiding back surface exposure while maintaining manufacturing feasibility
Solution Approach 2:
The patent applies preliminary action by forming the resist layer on the first semiconductor layer before performing the etching/removal process. This preliminary resist formation step allows the manufacturing process to proceed in a controlled manner, where the resist pattern is established first, then used as a mask during etching. This prevents uncontrolled removal of the first semiconductor layer and avoids exposing the back surface, thereby preserving carrier lifetime while enabling systematic manufacturing
2Reliability
If the first semiconductor layer is left in sea shape or island shape in the second region, then the back surface exposure is suppressed improving carrier lifetime, but the manufacturing precision requirement increases
Solution Approach 1:
The resist layer serves as an intermediary that translates the desired sea-island pattern into a controllable manufacturing process. By forming the resist first and then using it as a mask during etching, the process achieves precise control over the first semiconductor layer removal. The resist pattern can be designed to create the desired sea-island configuration, and the etching process faithfully reproduces this pattern with high precision, thereby achieving both carrier lifetime preservation and manufacturing accuracy
Solution Approach 2:
The patent utilizes parameter changes in the etching process to achieve the desired pattern. By controlling etching parameters such as etching time, etchant concentration, and application method, the process transitions from complete removal to selective removal, creating the sea-island structure. This parameter control allows precise adjustment of how much first semiconductor layer remains in the second region, enabling the desired pattern while maintaining manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the solar cell's performance by improving carrier lifetime and simplifying the manufacturing process, leading to increased productivity and efficiency.
Implementation Method 1
a first semiconductor layer deposited on a first region as part of one principal surface side of the semiconductor substrate
Implementation Method 2
a first semiconductor layer deposited on a first region as part of one principal surface side of the semiconductor substrate
Implementation Method 3
a second semiconductor layer deposited on a second region as another part of the one principal surface side of the semiconductor substrate
Implementation Method 4
a second semiconductor layer deposited on a second region as another part of the one principal surface side of the semiconductor substrate
Implementation Method 5
a semiconductor substrate; a first semiconductor layer deposited on a first region as part of one principal surface side of the semiconductor substrate
Data Source
AI summary
A solar cell for achieving an increase in performance. The solar cell is a back junction solar cell comprising a semiconductor substrate, first semiconductor layers stacked in a first region which is a part of the back side of the semiconductor substrate, and second semiconductor layers stacked in a second region which is another part of the back side of the semiconductor substrate. In the second region, the first semiconductor layers are present in some parts between the semiconductor substrate and the second semiconductor layers, wherein the first semiconductor layers comprise sea shapes in a sea-island structure.