Semiconductor Devices TRIZ Cases
- YAlN Back-Barrier HEMTs for Electron Confinement and Pinch-Off
A YAlN back-barrier helps scaled HEMTs confine 2DEG electrons, improve pinch-off, avoid second channels, and limit thermal resistance.
- Binary Oxide Contact Layer for Low-Resistance Semiconductor Terminals
A binary oxide interlayer between the semiconductor layer and source/drain terminals cuts contact resistance using standard CVD or ALD steps.
- Nitride Semiconductor Gate Masking to Reduce Etch Leakage
Using the gate electrode as the etch mask avoids photoresist ashing damage on the barrier layer and helps cut leakage current.
- HEMT Electrode Layout With Direct 2-DEG Contact for Lower Resistance
By exposing the 2-DEG at the surface for direct source and drain contact, this HEMT case cuts resistance and improves frequency response.
- Lateral PNP Emitter Ring Layout for Higher Current Density
Multiple emitter regions inside a collector ring boost lateral PNP current handling while cutting silicon area and current gain loss.
- Solar Cell Eutectic Contact Layer for Low-Resistance Textured Emitters
Mixed-shape conductive particles in a eutectic contact layer cut emitter resistance while preserving optical absorption and limiting corrosion.
- Nitride HEMT Buffer Structure for Dynamic On-Resistance Peaks
A segmented nitride buffer and downward S/D electrode contact suppress dynamic on-resistance peaks and improve HEMT yield.
- Conductive Plate Strained Transistor for Breakdown and On-Resistance
A conductive plate below the ILD restores the RESURF field and adds channel strain, raising breakdown voltage while lowering on-resistance.
- Compensation Layer Display Structure for Under-Panel Components
A metal pattern layer with slit patterns improves transmittance and planarity, letting displays show images above integrated sensors or cameras.
- Self-Aligned Ferroelectric FinFET Capacitor for Capacitance Balance
A ferroelectric capacitor formed directly on a FinFET gate balances capacitance, lowers voltage, and helps prevent dielectric breakdown.
- HBT Base Dopant Profile Control Using Segmented Epitaxial Layers
Segmented epitaxial base layers confine phosphorus in an HBT, reducing segregation and keeping the PN junction inside the SiGe sub-layer.
- Hemispherical SPAD Photodiode Layout for High Fill Factor
A buried hemispherical region and nested core shrink the guard ring in miniaturized SPADs while raising fill factor and photon detection.
- GaN HEMT Asymmetric Field Plates for Breakdown Voltage
A longer drain than source field plate evens GaN HEMT electric fields, raising breakdown voltage and reducing drain leakage.
- p-GaN HEMT Field Plate Layout for Leakage and Breakdown Control
A stepped p-GaN gate and non-overlapping field plate curb leakage, raise breakdown voltage, and keep the HEMT normally off.
- Slot Via Rails for Full Source/Drain Contact Landing
Elongated slot vias and via rails improve source/drain contact landing despite overlay shift, cutting resistance and gate shorting.
- LED Reflective Layer Structure for Short-Wave Light Extraction
Using an aluminum reflective layer without an adhesion layer boosts short-wave LED reflectivity and reduces absorption losses.
- GaN FET Barrier Structure for Independent 2DEG and Threshold Control
Segmented AlGaN barriers and p-GaN gates let this GaN FET tune 2DEG and threshold voltage independently while improving dynamic immunity.
- SiC Power Semiconductor Structure With JFET Contact for Lower On-Resistance
A shielded JFET contact structure adds current paths and full depletion to cut SiC on-resistance without sacrificing normally-off behavior.
- Method of operating a power transistor formed by a plurality of transistor cells electrically connected in parallel
A ferroelectric gate dielectric self-limits drain current in parallel power transistors, improving short-circuit protection without added sensors.
- Recessed Growth Substrate Structure for Lower RF Loss
Recesses in the growth substrate block parasitic RF circuits, while lateral epitaxial buffer overgrowth lowers dislocation density and RF loss.
- GaN HEMT Contact Implant Scheme for Lower Contact Resistance
A two-stage DSS implant tunes GaN HEMT source-drain doping to cut contact and tunneling resistance without harming the 2DEG.
- TRIAC Gate Layout for Sensitivity and Commutation Trade-Off
A localized fifth N-type region adds serial resistance in the gate path, lowering trigger current while improving TRIAC commutation at high voltage.
- Vertical Fin BJT Structure for High-Density Low-Leakage Semiconductors
A vertical fin BJT layout expands PN junction and contact area to raise current density while reducing leakage in scaled semiconductors.
- Photovoltaic Cell Texture Layout for Lower Recombination Loss
Segmented front textures and selective tunneling layers improve light use while limiting carrier recombination and parasitic absorption.
- Extended MOS Gate Structure for Leakage Control and Space Efficiency
By extending gate oxide or metal beyond the active region, this case controls voltage distribution to suppress gate-off leakage and save chip area.
- Mie Photo Sensor Resonance for Small-Pixel Imaging
Mie scattering localizes carrier generation in semiconductor mesas, enabling smaller pixels with higher light sensitivity and dynamic range.
- GaN Gate Recess Structure for Lower Leakage Power Transistors
A recessed p-doped GaN gate with limited drain-side extension cuts gate leakage while preserving current handling and switching speed.
- Lateral Bipolar Transistor Structure for Lower Parasitic Capacitance
A self-aligned FDSOI lateral bipolar structure uses a SiGe base and raised emitter-collector regions to cut parasitic capacitance and base resistance.
- Semiconductor Contact Structure With Conformal Interfacial Layers
Rapid thermal treatment forms an interfacial layer between barrier and adhesion films, enabling conformal thin contacts in high-aspect-ratio recesses.
- Nitride Gate Structure Integrating HEMT and Schottky Junctions
A metal-semiconductor gate junction combines HEMT and Schottky diode functions in one nitride structure, saving area while boosting saturation current.
- Trench Power Semiconductor Isolation Structure for Single-Chip Integration
Floating-potential polysilicon isolation trenches separate adjacent active devices on one chip, cutting extra oxide processing, cost, and time.
- Auxiliary Electrode Patterning for Large High-Definition OLED Displays
An auxiliary pattern between the connection pattern and second electrode cuts contact resistance, enabling larger high-definition OLED displays at lower cost.
- FinFET Sidewall Spacer Cavity for Lower Parasitic Capacitance
An air-filled cavity between FinFET sidewall spacers cuts parasitic capacitance while protecting the gate and improving electrostatic control.
- LDMOS Dual-Trench Isolation for Low On-Resistance and High Voltage
Adjacent deep and shallow isolation trenches help LDMOS devices cut on-resistance while maintaining withstand voltage with simpler processing.
- Power Semiconductor Runner Layout for Thermal Strain Relief
Segmented runner electrodes, vias, and non-parallel metal paths reduce thermal strain, cracking, and delamination in power semiconductor dies.
- Optoelectronic Semiconductor Chip Layers for Low-Loss Light Extraction
A low-absorption output coupling layer paired with a conductive current spreading layer boosts primary radiation extraction while limiting loss.
- AgAu Reflective Contact Layer for Micro-LED Transfer Yield
An AgAu reflective contact layer with varied ohmic contacts improves micro-LED self-assembly yield, reflectivity, and electrical reliability.
- High-Voltage Transistor Field Plate Layout for Hot Carrier Control
An equipotential field plate over a continuous insulating layer spreads electric fields, reducing hot carrier effects while preserving breakdown voltage.
- Photovoltaic Cell Texture Layout for Light Absorption and Low Recombination
Region-specific pyramid textures and tunneling layers improve light capture while reducing interface defects and carrier recombination.
- HEMT Gate Spacer Layout for Dense, Alignment-Tolerant Scaling
Dielectric spacers define self-aligned HEMT gate spacing, easing lithography limits while improving die area use and lowering gate resistance.
- LED Light-Collecting Lens Structure for Narrow Emission Angles
Segmented convex lenses over separated emission regions collect and redirect LED light to cut stray loss and narrow the output angle.
- Segmented Trench Semiconductor Layout for Faster Reverse Recovery
Separated trench portions and inter-trench doping reduce electric field concentration, lower ON voltage, and speed reverse recovery.
- Angled Gate Trenches With Partial Shielding for Power MOSFETs
Partial deep shielding along angled gate trench sidewalls lowers gate oxide electric field stress while preserving transistor channel area.
- Silicide Direct Contact Structure for Low-Resistance Memory Cells
A silicide lower contact and metal upper layer cut memory-cell contact resistance and defects while supporting dense bit-line integration.
- AlGaN Semiconductor Layout for Drain-Side Trap Suppression
Selective fluorine placement near the drain suppresses traps while keeping on-resistance low and device characteristics stable under high electric fields.
- 2D Channel FET Contact Structure With Lower Schottky Barrier
A channel-last chalcogen treatment forms a gradient TMC contact region that lowers Schottky barrier height and contact resistance in 2D FETs.
- Vertical FRAM Cell Structure for Higher Current Density
A vertical channel in FRAM raises cell current without enlarging footprint, while shared lines help preserve high memory density.
- Color Conversion Layer Structure for Thin Light-Emitting Packages
A through-hole reflective sheet and void-free resin color layer improve chromaticity in thin light-emitting packages.
- Dielectric Layer Stack for Directional Wavelength-Converted Emitters
Selective angle- and wavelength-dependent dielectric layers improve directional emission and compactness in wavelength-converted semiconductor light sources.