FinFET Sidewall Spacer Cavity for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional FinFET semiconductor structures face challenges in improving performance due to limitations in electrostatic control and increased parasitic capacitance as device sizes shrink, leading to poor device performance and potential damage during manufacturing processes.
Innovation Solution
A semiconductor structure and fabrication method involving a sidewall spacer structure with a first sidewall spacer, a second sidewall spacer, and a cavity between them, where the first sidewall spacer protects the gate structure and the cavity reduces parasitic capacitance by allowing air to fill, thereby enhancing electrostatic control and reducing damage during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase integration density, then device density is improved, but parasitic capacitance increases and electrostatic control deteriorates
Solution Approach 1:
The gate structure is segmented into multiple sections with different work function materials (first gate section with first work function material, second gate section with second work function material), allowing independent optimization of electrostatic control for different device regions while maintaining high integration density
Solution Approach 2:
Different work function materials are applied to different gate sections to create local electrical characteristics optimized for specific device types (e.g., NFET vs PFET), improving electrostatic control without increasing overall parasitic capacitance
2Quantity of substance
If device size is reduced to increase integration density, then device density is improved, but electrostatic control deteriorates
Solution Approach 1:
The gate is divided into multiple sections with different work function materials, enabling tailored electrostatic control for each device region while maintaining scaled dimensions for high density
Solution Approach 2:
The work function parameter is varied across different gate sections by using different materials, optimizing electrostatic control characteristics for each device type without changing the physical device dimensions
3Ease of manufacture
If conventional FinFET structure is used, then manufacturing process is simple, but device performance is poor due to increased parasitic capacitance
Solution Approach 1:
The gate structure is segmented into multiple sections with different work function materials, improving device performance by reducing parasitic capacitance while using standard FinFET fabrication processes
Solution Approach 2:
The gate structure uses composite materials with different work functions in different sections, achieving superior electrical performance while maintaining compatibility with existing manufacturing processes
Data Source
AI summary
A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate, a gate structure over the substrate, and a sidewall spacer structure located on a sidewall surface of the gate structure. The sidewall spacer structure includes a first sidewall spacer, a second sidewall spacer, and a cavity located between the first sidewall spacer and the second sidewall spacer. The first sidewall spacer is located on the sidewall surface of the gate structure. A top surface of the cavity is above a top surface of the gate structure, and a bottom surface of the cavity is coplanar with a bottom surface of the gate structure. The semiconductor structure also includes a source and drain plug located over the substrate on each side of the gate structure. The source and drain plug is located on a sidewall surface of the second sidewall spacer.