LDMOS Dual-Trench Isolation for Low On-Resistance and High Voltage
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Solution Overview
Problem
LDMOS transistors with shallow trench isolation face challenges in achieving low on-resistance while maintaining high withstand voltage, as the current path in the offset layer is lengthened by the isolation, leading to increased resistance, particularly at lower voltage levels, and complicating the manufacturing process.
Innovation Solution
The semiconductor device incorporates trenches of different depths arranged adjacently in the gate width direction, with a deep trench for high withstand voltage and a shallower trench for low withstand voltage, embedding a dielectric film in both to form a two-level element isolation structure, which reduces on-resistance and simplifies the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a shallow trench isolation is placed in the offset layer to achieve high withstand voltage, then the withstand voltage is improved, but the current path length increases leading to higher on-resistance
Solution Approach 1:
The trench isolation is divided into two segments: a first trench extending from the surface to a first depth, and a second trench extending from the surface to a second depth (shallower than the first). This segmentation allows the current to flow through multiple paths, reducing the effective current path length through the offset layer while still providing adequate voltage blocking capability.
Solution Approach 2:
Different regions of the trench isolation have different depths tailored to their specific functions. The first trench provides deeper isolation where voltage blocking is critical, while the second trench provides shallower isolation where current flow needs to be maintained. This local differentiation optimizes both withstand voltage and on-resistance characteristics.
2Reliability
If a deep trench isolation is used to reduce on-resistance by shortening current path, then on-resistance is improved, but withstand voltage capability deteriorates
Solution Approach 1:
The dual-trench structure segments the isolation function into two depth levels. The deeper first trench handles the voltage blocking requirement, while the shallower second trench maintains current flow paths, thus simultaneously achieving both low on-resistance and high withstand voltage capability.
Solution Approach 2:
The solution moves from a single-depth (one-dimensional) trench structure to a multi-depth (two-dimensional in the vertical dimension) trench structure. This dimensional change allows independent optimization of voltage blocking and current flow paths at different depths.
3Adaptability or versatility
If separate deep STI and shallow STI are formed on the same chip, then different voltage requirements are met, but the manufacturing process becomes complicated
Solution Approach 1:
The formation of deep and shallow trenches is merged into a single integrated manufacturing process sequence. Both trench types are formed using coordinated photolithography and etching steps, eliminating the need for separate processing lines and reducing overall process complexity.
Solution Approach 2:
The manufacturing process is designed to be universal, capable of forming both deep and shallow trenches using the same equipment and material layers. The process can accommodate different voltage class requirements without requiring dedicated process lines, thus reducing complexity while maintaining versatility.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.