HEMT Electrode Layout With Direct 2-DEG Contact for Lower Resistance
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Solution Overview
Problem
High-electron-mobility transistors (HEMTs) face limitations in current and frequency characteristics due to resistance issues in the formation of source and drain electrodes, which affect the electrical performance of the devices.
Innovation Solution
A method of manufacturing HEMTs that involves forming a transition layer and a semiconductor layer on a substrate, etching a barrier layer region, and creating source and drain electrodes directly on the 2-dimensional electron gas (2-DEG) layer exposed at the surface, followed by a passivation layer and a gate electrode, with the electrodes being electrically connected to minimize resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source electrode and drain electrode are formed using conventional methods, then device structure is complete, but resistance is high which limits current and frequency characteristics
Solution Approach 1:
The patent exposes the 2-DEG layer at the surface by etching the semiconductor layer, transitioning from a planar electrode formation to a vertical/dimensional approach where electrodes contact the 2-DEG layer directly at the surface, reducing the conduction path and resistance
Solution Approach 2:
The patent extracts the 2-DEG layer from within the semiconductor bulk by etching away the semiconductor layer above it, making the 2-DEG layer accessible at the surface for direct electrode contact, thereby eliminating intermediate resistive layers
2Object-affected harmful factors
If 2-DEG layer is exposed at surface for direct electrode connection, then resistance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the semiconductor layer by etching it to form a barrier layer region with exposed 2-DEG layer, creating distinct functional zones that enable direct electrode contact while maintaining the underlying heterostructure
Solution Approach 2:
The patent performs preliminary etching of the semiconductor layer to expose the 2-DEG layer before forming the source and drain electrodes, preparing the structure in advance to facilitate direct electrode connection and reduce subsequent processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistance and enhances the frequency characteristic of HEMTs, improving their electrical performance by directly connecting the 2-DEG layer to the electrodes and optimizing the electrode formation process.
Implementation Method 1
Based on band discontinuity occurring due to a band gap difference between semiconductors and polarization caused by the hetero semiconductor junction structure, a 2-dimensional electron gas (2-DEG) layer is formed in a heterojunction interface
Implementation Method 2
Based on band discontinuity occurring due to a band gap difference between semiconductors and polarization caused by the hetero semiconductor junction structure, a 2-dimensional electron gas (2-DEG) layer is formed in a heterojunction interface
Implementation Method 3
diffusing the formed first and second metal patterns into the semiconductor layer and the barrier layer through a rapid thermal process
Data Source
AI summary
A method of manufacturing a high-electron-mobility transistor device is provided. The method includes sequentially forming a transition layer and a semiconductor layer on a substrate, etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region, forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer, forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer, and forming a gate electrode on the upward exposed barrier layer.