TRIAC Gate Layout for Sensitivity and Commutation Trade-Off
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Solution Overview
Problem
Conventional TRIAC designs face a tradeoff between commutation and sensitivity due to increased semiconductor thickness for higher voltage handling, leading to reduced sensitivity and inadequate commutation performance, especially in high voltage applications.
Innovation Solution
The TRIAC design incorporates a plurality of semiconductor regions with specific doping levels and configurations, including a fifth N-type region that acts as a serial resistance between the gate and main terminal contacts, improving sensitivity and commutation without degrading performance in other operating conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the thickness of semiconductor material is increased to withstand higher voltages, then voltage handling capability is improved, but sensitivity and commutation performance deteriorate
Solution Approach 1:
The patent applies local quality by creating a fifth N-type region with high doping concentration specifically in the gate-cathode path area, while maintaining other regions with their original doping levels. This localized modification improves sensitivity and commutation performance without requiring a reduction in overall semiconductor thickness, thus resolving the contradiction between voltage handling capability and sensitivity/commutation performance.
Solution Approach 2:
The patent changes the doping concentration parameter by introducing a fifth N-type region with high doping concentration (10^19 to 10^21 atoms/cm³) in the gate-cathode path. This parameter change reduces the resistance in the gate trigger path, improving sensitivity and commutation performance while maintaining the thicker semiconductor structure needed for high voltage handling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances sensitivity and commutation performance in certain operating conditions, particularly in the I-V+ region, by lowering the gate trigger current and increasing the critical rate of rise of off-state current, making it suitable for high-voltage applications.
Implementation Method 1
The fifth N-type region is positioned between the first N-type region and the fourth N-type region, serving as a serial resistance between the gate terminal contact and the first main terminal contact
Data Source
AI summary
A TRIAC features first and second main-terminal contacts, and a gate terminal contact, with multiple semiconductor regions stacked along a first-axis and extending laterally along an intersecting second-axis that defines first, second, and middle regions. The semiconductor regions include a third N-type region overlying the second main-terminal contact, a second P-type region overlying the second main-terminal contact, a second N-type region overlying the second P-type region, a first P-type region overlying the second N-type region, a first N-type region partially overlying the first P-type region, a fourth N-type region partially overlying the first P-type region, and a fifth N-type region partially overlying the first P-type region. The first main-terminal contact is partly on the first N-type region in the first region and on the first P-type region in the second region, while the gate terminal contact is partly on both the first P-type region and the fourth N-type region.