Power Semiconductor Runner Layout for Thermal Strain Relief
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Solution Overview
Problem
Power semiconductor devices experience significant strain due to large temperature swings, leading to cracking, delamination, and failure, necessitating a reduction in strain to enhance reliability.
Innovation Solution
The design incorporates a runner electrode with strain relief regions, segmented runner vias, and non-parallel metal runner paths to distribute strain more evenly, reducing the overall strain on the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the runner electrode is provided continuously along the perimeter of the active region, then electrical connectivity is improved, but strain on the device increases leading to cracking and delamination
Solution Approach 1:
The runner electrode is divided into multiple segments along its path, with gaps between segments. This segmentation reduces the continuous strain that would otherwise cause cracking and delamination, while still maintaining adequate electrical connectivity through the distributed electrode segments.
2Ease of manufacture
If the runner via is provided as a continuous opening, then manufacturing is simplified, but strain concentration occurs at the via edges
Solution Approach 1:
The runner via is segmented into multiple discrete openings rather than one continuous opening. This segmentation distributes the strain concentration that would occur at via edges, reducing the risk of cracking while still providing the necessary electrical connection through the insulating layer.
3Ease of manufacture
If the metal runner path is parallel to the runner electrode path, then manufacturing alignment is improved, but strain is not effectively reduced
Solution Approach 1:
The metal runner path is designed to be non-parallel to the runner electrode path, creating an asymmetric layout. This asymmetric configuration helps distribute strain more evenly across the device structure, preventing strain concentration that would occur with parallel paths, while still maintaining manufacturable alignment tolerances.
Data Source
AI summary
Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.