Slot Via Rails for Full Source/Drain Contact Landing
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Solution Overview
Problem
As semiconductor feature sizes decrease, overlay and alignment control issues during the formation of source/drain vias and metal contacts lead to increased contact resistance and potential shorting between source/drain vias and metal gates, causing partial contact and leakage problems in high-density integrated circuits.
Innovation Solution
The formation of elongated slot vias and via rails that make full surface contact with source/drain metal contacts, along with the use of a contact etch stop layer to prevent undesired etching over metal gates, and eliminating shared butted contacts in favor of direct landing on gate vias, ensuring proper insulation and full contact landing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain via formation methods are used, then manufacturing process simplicity is maintained, but contact resistance increases and full contact landing cannot be ensured due to overlay misalignment
Solution Approach 1:
The patent transitions from circular via holes to elongated slot vias that extend in the x-direction. This dimensional change allows the via to span across multiple potential overlay misalignment positions, ensuring that at least one end of the slot via achieves full contact with the source/drain metal contact regardless of alignment variations.
Solution Approach 2:
The slot via structure can be viewed as segmented into multiple contact zones along its length. Even if one portion misses the contact due to overlay error, other segments along the elongated structure can still establish electrical connection, providing redundancy and ensuring reliable contact.
2Reliability
If conventional via formation is used, then process complexity is minimized, but shorting between source/drain vias and metal gates occurs due to overlay shift
Solution Approach 1:
The patent introduces a dielectric cap layer that sits between the metal gate and the slot via. This intermediary layer provides electrical isolation, preventing direct contact and potential shorting between the conductive via and the metal gate, while still allowing the via to achieve full contact landing on the source/drain contact.
Solution Approach 2:
By extending the via in the x-direction to create a slot shape, the via width in the y-direction (where alignment sensitivity is highest) is reduced. This dimensional transformation decreases the probability of the via overlapping with the metal gate, thereby preventing shorting.
3Reliability
If shared butted contacts are eliminated, then insulation between source/drain features and metal gates is improved, but manufacturing steps increase
Solution Approach 1:
The patent combines multiple functions into the slot via structure itself. The elongated via simultaneously provides electrical connection to the source/drain contact and physical separation from the metal gate, eliminating the need for separate shared butted contact structures while maintaining proper insulation.
Solution Approach 2:
The slot via serves multiple purposes: it provides the electrical connection path, acts as a spacer maintaining isolation from the gate, and defines the contact landing zone. This multi-functionality reduces the need for additional specialized structures like shared butted contacts.
Data Source
AI summary
One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes receiving a workpiece having a first metal gate stack over a first channel region, a second metal gate stack over a second channel region, a source/drain (S/D) feature between the first and second channel regions, and an S/D contact over the S/D feature. First and second dielectric caps are formed over the first and second metal gate stacks and a contact etch stop layer (CESL) is formed over the S/D contact and over the first and second dielectric caps. An interlayer dielectric (ILD) layer is formed over the CESL and an S/D via trench is formed through the ILD layer and the CESL. An S/D via is formed in the S/D via trench, making full surface contact with the S/D contact and partial surface contact with the first and second dielectric caps.