p-GaN HEMT Field Plate Layout for Leakage and Breakdown Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-electron-mobility transistors (HEMTs) using nitride semiconductors face challenges in achieving a normally-off state, which is crucial for fail-safe power devices, as existing designs struggle to maintain a blocked current path at zero bias and suffer from leakage currents and insulation breakdown under high voltage.
Innovation Solution
The nitride semiconductor device incorporates a GaN electron transit layer and an AlGaN electron supply layer with a p-type GaN gate layer containing acceptor impurities, along with a stepped gate structure and a field plate electrode on the passivation layer, to create a two-dimensional electron gas and mitigate electric field concentration, ensuring a normally-off state and increased breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type GaN gate layer is used to interrupt the channel and achieve normally-off state, then the HEMT can be turned off at zero bias, but gate leakage current increases under high voltage
Solution Approach 1:
The gate structure is divided into multiple segments: a p-type GaN gate layer for establishing the normally-off state, and a field plate electrode structure that segments the electric field distribution. This segmentation allows the gate to maintain its blocking function while reducing leakage through distributed field management.
Solution Approach 2:
A field plate electrode is introduced as an intermediary element between the gate and the drain region. This field plate acts as a mediator that shapes and distributes the electric field, preventing direct high-voltage stress on the p-type gate and thereby reducing gate leakage current while maintaining the normally-off characteristic.
2Device complexity
If the gate structure is simplified to reduce complexity, then manufacturing becomes easier, but electric field concentration increases causing insulation breakdown
Solution Approach 1:
The gate structure transitions from a simple planar configuration to a three-dimensional stepped configuration with multiple levels. This dimensional change allows the electric field to be distributed across multiple surfaces and volumes, reducing field concentration at any single point while maintaining overall structural manageability.
Solution Approach 2:
The stepped gate structure introduces curved surfaces and rounded transitions instead of sharp corners. This curvature distributes electric field lines more evenly across the gate surfaces, preventing field concentration at sharp edges and thereby increasing breakdown voltage without significantly increasing manufacturing complexity.
3Reliability
If the gate layer completely overlaps the drain electrode to maximize field control, then breakdown voltage increases, but parasitic capacitance increases reducing switching speed
Solution Approach 1:
The field plate electrode is designed with non-uniform dimensions, being wider in regions where field control is critical and narrower or absent in regions where speed is prioritized. This local variation in geometry allows optimization of both breakdown voltage and switching speed in different spatial regions of the device.
Solution Approach 2:
Instead of complete overlap between the field plate and drain electrode, a partial overlap is implemented. This partial action provides sufficient field control to increase breakdown voltage while limiting the overlapping area to minimize parasitic capacitance and maintain switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces gate leakage current, increases gate and breakdown voltages, and minimizes parasitic capacitance, enhancing the reliability and performance of nitride semiconductor HEMTs in power devices by maintaining a blocked current path at zero bias and preventing insulation breakdown.
Implementation Method 1
two-dimensional electron gas (2DEG) generated in the electron transit layer in the vicinity of a heterojunction interface between the electron transit layer and the electron supply layer
Implementation Method 2
a GaN layer (p-type GaN layer) containing acceptor impurities and arranged under a gate electrode to interrupt the channel formed by 2DEG
Data Source
AI summary
A nitride semiconductor device includes an electron transit layer, an electron supply layer, a gate layer containing acceptor impurities, a gate electrode, a passivation layer, a source electrode, a drain electrode, and a field plate electrode. The field plate electrode is located on the passivation layer between the gate layer and the drain electrode. The gate layer includes a ridge where the gate electrode is located, a source-side extension extending from the ridge, and a drain-side extension extending from the ridge to a side opposite to the source-side extension. The passivation layer includes a field plate non-overlapping region that does not overlap the field plate electrode and is located immediately above the drain-side extension.