Vertical FRAM Cell Structure for Higher Current Density
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Solution Overview
Problem
The challenge in scaling down FRAM memory devices is due to the requirement for a larger channel length to increase cell current, which results in an enlarged footprint, making it difficult to maintain the non-volatility of ferroelectric random-access memory cells.
Innovation Solution
The implementation of a vertical channel layer instead of a horizontal channel layer allows for an increase in gate height without expanding the memory cell footprint, enhancing cell current without impacting the cell size, and optimizing the memory cell density by sharing source and bit lines between adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a horizontal channel layer is used to increase cell current by increasing channel length, then the cell current increases, but the memory cell footprint enlarges
Solution Approach 1:
The patent transitions from a horizontal channel layer to a vertical channel layer, changing the spatial dimension of the current path. This vertical configuration allows the channel length to extend in the vertical direction rather than horizontally, enabling increased channel length without proportionally increasing the planar footprint of the memory cell. The vertical channel layer is formed between source and drain regions that are positioned vertically, creating a three-dimensional current path that resolves the contradiction between current magnitude and cell area.
2Power
If the channel length is increased to increase cell current, then the cell current increases, but the memory cell density decreases
Solution Approach 1:
By implementing a vertical channel layer structure, the patent enables the channel length to be extended in the vertical dimension while maintaining a compact planar footprint. This allows multiple memory cells to be packed more densely in the horizontal plane, as each cell occupies less horizontal space despite having a longer vertical channel for higher current. The vertical stacking approach increases the number of cells per unit area, thereby improving memory cell density while preserving the required current levels.
Solution Approach 2:
The vertical channel layer structure allows for a nested arrangement where the channel is positioned within a three-dimensional configuration between source and drain regions. This nested vertical structure enables more efficient space utilization, allowing adjacent cells to share common structures such as bit lines and word lines, thereby increasing the overall density of the memory array while maintaining adequate current through the vertical channel path.
Data Source
AI summary
A memory device comprises a word line, a gate dielectric layer, a channel layer, and a resistance-switchable element. The word line is over a substrate. The gate dielectric layer contacts a sidewall of the word line. The channel layer contacts the gate dielectric layer. The resistance-switchable element contacts a sidewall of the channel layer. The resistance-switchable element extends vertically beyond the sidewall of the word line.