Nitride HEMT Buffer Structure for Dynamic On-Resistance Peaks

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Solution Overview

Problem

High electron mobility transistors (HEMTs) face a dynamic on-resistance peak issue, which affects their performance and yield rate, particularly in high power and frequency applications, due to parasitic p-n junction diodes and defects in the buffer layer.

Innovation Solution

A nitride-based semiconductor device configuration is introduced, featuring a substrate with a buffer layer, a first and second nitride-based semiconductor layer, and source/drain electrodes with specific profiles and a shield layer to reduce the dynamic on-resistance peak by forming a heterojunction and electrical isolation region, respectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional buffer layer structure is used in HEMT devices, then the manufacturing process is simple, but parasitic p-n junction diodes and defects form causing dynamic on-resistance peak issues

Engineering Contradiction:
Improvedynamic on-resistance performanceVSAvoidbuffer layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The buffer layer is segmented into multiple distinct layers: a first buffer layer (AlGaN) and a second buffer layer (GaN), each with different compositions and functions. This segmentation allows the first buffer layer to provide lattice matching while the second buffer layer reduces dislocation density, thereby eliminating parasitic p-n junction diodes and resolving the dynamic on-resistance peak issue without excessive complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the buffer structure are assigned different local qualities: the first buffer layer has specific Al composition (0.1-0.3) optimized for lattice matching, while the second buffer layer is AlGaN-free GaN optimized for defect reduction. This local quality differentiation enables each layer to perform its specific function optimally, improving overall device reliability

Inventive Principle:
Principle #3Local quality

2Reliability

If the source/drain electrode extends downward to contact the buffer layer, then the dynamic on-resistance peak is reduced, but the manufacturing precision requirement increases

Engineering Contradiction:
Improvedynamic on-resistanceVSAvoidelectrode positioning
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The source/drain electrode is designed to extend downward in advance to contact the first buffer layer before the final device assembly. This preliminary action of extending the electrode to reach the buffer layer ensures direct electrical contact that eliminates the dynamic on-resistance peak, while the downward extension path is pre-planned in the device structure to manage manufacturing precision requirements

Inventive Principle:
Principle #10Preliminary action

3Reliability

If heterostructure layers with different bandgaps are used, then high electron mobility is achieved, but defects in the buffer layer cause yield rate issues

Engineering Contradiction:
Improveelectron mobilityVSAvoidyield rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The first buffer layer acts as an intermediary between the substrate and the second buffer layer. It provides lattice matching to reduce dislocation density, while the second buffer layer (AlGaN-free GaN) further reduces defects. This intermediary structure maintains the heterostructure needed for high electron mobility while significantly improving yield rate by reducing buffer layer defects

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The configuration improves the dynamic on-resistance peak issue, enhances the yield rate of semiconductor device manufacturing, and maintains compatibility for high electron mobility transistor (HEMT) applications.

Implementation Method 1

The HEMT utilizes a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region

Methodology Applied
Scientific EffectHeterojunction:

Implementation Method 2

The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a two-dimensional electron gas (2DEG) region

Methodology Applied
Scientific EffectBandgap difference:

Implementation Method 3

High electron mobility transistors (HEMTs) face a dynamic on-resistance peak issue, which affects their performance and yield rate, particularly in high power and frequency applications, due to parasitic p-n junction diodes and defects in the buffer layer

Methodology Applied
Scientific EffectParasitic p-n junction: Diode

Data Source

PatentUS12166102B2Semiconductor device and method for manufacturing the same
Publication Date: 2024.12.10 INNOSCIENCE (SUZHOU) TECH CO LTD
  • US12166102B2 patent drawing
  • US12166102B2 patent drawing
  • US12166102B2 patent drawing

AI summary

A nitride-based semiconductor device includes a substrate, a buffer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a S/D electrode, a second S/D electrode, and a gate electrode. The buffer is disposed over the substrate and includes at least one layer of a nitride-based semiconductor compound doped with an acceptor at a top-most portion of the buffer. The first and second nitride-based semiconductor layers are disposed over the buffer. The first S/D electrode is disposed over the second nitride-based semiconductor layer, in which the first S/D electrode extends downward to a position lower than the first nitride-based semiconductor layer, so as to form at least one first interface with the top-most portion of the buffer, making contact with the at least one layer of the nitride-based semiconductor compound. The second S/D electrode and the gate electrode are disposed over the second nitride-based semiconductor layer.