GaN Gate Recess Structure for Lower Leakage Power Transistors

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Solution Overview

Problem

Conventional transistor devices for power electronic applications face challenges in reducing gate leakage current, particularly due to the design of field plates which often increase leakage when their extensions exceed a certain length, leading to inefficiencies in current handling and switching times.

Innovation Solution

A Group III nitride-based transistor device with a gate structure featuring a p-doped Group III nitride layer arranged in a recess with a shorter extension towards the drain, potentially eliminating any extension, and a longer extension towards the source, which reduces gate leakage current by minimizing potential differences between the channel and gate structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If field plate extension length is increased to improve current handling, then current handling capability is improved, but gate leakage current increases

Engineering Contradiction:
Improvecurrent handling capabilityVSAvoidgate leakage current
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies different doping types to different regions of the field plate structure. The region extending towards the drain is doped with first dopant (n-type) while the region extending towards the source is doped with second dopant (p-type), creating local quality variations that reduce gate leakage current while maintaining current handling capability

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent creates an asymmetric doping configuration where the field plate has different doping characteristics on opposite sides. The drain-side extension uses one dopant type while the source-side extension uses another, breaking the symmetry to optimize both current handling and leakage reduction in different regions

Inventive Principle:
Principle #4Asymmetry

2Speed

If field plate extension length is increased to improve switching speed, then switching speed is improved, but gate leakage current increases

Engineering Contradiction:
Improveswitching speedVSAvoidgate leakage current
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent applies different doping types to different regions of the field plate structure. The region extending towards the drain is doped with first dopant (n-type) while the region extending towards the source is doped with second dopant (p-type), creating local quality variations that reduce gate leakage current while maintaining current handling capability

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent creates an asymmetric doping configuration where the field plate has different doping characteristics on opposite sides. The drain-side extension uses one dopant type while the source-side extension uses another, breaking the symmetry to optimize both current handling and leakage reduction in different regions

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration surprisingly reduces gate leakage current, contrary to expectations, by addressing the issue of hole current flow at the interface between the nitride barrier and insulation layer, thereby enhancing the device's performance in current handling and switching speed.

Implementation Method 1

This configuration surprisingly reduces gate leakage current, contrary to expectations, by addressing the issue of hole current flow at the interface between the nitride barrier and insulation layer

Methodology Applied
Scientific EffectHole current flow: Conduction (electrical)

Data Source

PatentUS12159918B2Group III nitride-based transistor device
Publication Date: 2024.12.03 INFINEON TECH AUSTRIA AG
  • US12159918B2 patent drawing
  • US12159918B2 patent drawing
  • US12159918B2 patent drawing

AI summary

In an embodiment, a Group III nitride-based transistor device, includes a first Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm≤ld≤200 nm.