Silicide Direct Contact Structure for Low-Resistance Memory Cells

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Solution Overview

Problem

As semiconductor memory devices become more integrated, manufacturing processes become increasingly complex due to finer circuits and smaller design rules, leading to challenges in creating effective contact structures that reduce contact resistance and defects.

Innovation Solution

A semiconductor memory device is designed with a direct contact structure that includes a lower layer of semiconductor silicide and an upper metal layer, connected by bit lines and word lines, with a buried contact system that enhances contact area and reduces resistance through the use of landing pads, and a manufacturing method that forms these contacts by etching and silicidation processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional contact structure is used in highly integrated semiconductor memory devices, then manufacturing complexity increases, but contact resistance and defects worsen

Engineering Contradiction:
Improvecontact resistanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The contact structure is divided into multiple distinct layers: a lower layer (first contact layer) and an upper layer (second contact layer). This segmentation allows each layer to be optimized for its specific function - the lower layer for reducing contact resistance with the substrate and the upper layer for providing a stable platform for bit line connections, thereby improving overall contact reliability without overwhelming manufacturing complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The contact structure employs composite material composition with different materials in the lower and upper layers. The lower layer uses materials specifically selected for low contact resistance with the substrate, while the upper layer uses materials optimized for mechanical stability and electrical connection with bit lines. This composite approach resolves the contradiction by achieving reliable electrical contact through material optimization rather than process complexity

Inventive Principle:
Principle #40Composite materials

2Productivity

If circuit design rules are reduced for higher integration, then device density improves, but manufacturing precision requirements worsen

Engineering Contradiction:
Improvedevice integration densityVSAvoidcontact structure fabrication precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The lower contact layer is formed first through preliminary actions including substrate preparation, formation of a recess, and deposition of contact material before the upper layer is added. This preliminary formation of the lower layer with its specific material properties and geometric configuration establishes a foundation that simplifies subsequent manufacturing steps, allowing higher integration density to be achieved without proportionally increasing manufacturing precision requirements

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Different regions of the contact structure have different material compositions and properties - the lower layer has materials optimized for substrate contact, while the upper layer has materials optimized for bit line connection. This local quality differentiation allows each region to perform its function effectively, enabling higher device density without requiring uniform high precision across the entire contact structure

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces contact resistance and defects by using a silicide-based direct contact structure and buried contact system, improving the performance and reliability of semiconductor memory devices.

Implementation Method 1

converting at least a portion of the lower layer into a silicide of the metal

Methodology Applied
Scientific EffectSilicidation: Chemical Bonding

Data Source

PatentUS20240397707A1Semiconductor memory device and manufacturing method thereof
Publication Date: 2024.11.28 SAMSUNG ELECTRONICS CO LTD
  • US20240397707A1 patent drawing
  • US20240397707A1 patent drawing
  • US20240397707A1 patent drawing

AI summary

A semiconductor memory device includes a substrate having a cell array area and a core area near the cell array area, the cell array area including a direct contact hole exposing an active region, a buried contact in the cell array area, the buried contact being connected to a storage element, a direct contact in the cell array area, the direct contact including an upper layer and a lower layer, the upper layer including a metal, and the lower layer being in the direct contact hole in direct contact with the active region and including a silicide of the metal, bit lines in contact with the upper layer of the direct contact, and word lines crossing the bit lines.