Binary Oxide Contact Layer for Low-Resistance Semiconductor Terminals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in achieving low contact resistance between semiconductor channel layers and source/drain terminals, which affects the overall performance of semiconductor devices.
Innovation Solution
The integration of a binary oxide layer between the semiconductor channel layer and the source/drain terminals, formed through deposition processes like CVD or ALD, helps in reducing contact resistance and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source/drain terminals are directly formed on the semiconductor channel layer, then the manufacturing process is simple, but the contact resistance is high
Solution Approach 1:
A binary oxide layer is introduced as an intermediary between the semiconductor channel layer and the source/drain terminals. This intermediate layer facilitates better electrical connection by reducing contact resistance, while the layer is subsequently removed in specific regions to allow direct contact where needed. The binary oxide layer acts as a temporary mediator that improves contact properties during formation.
Solution Approach 2:
The binary oxide layer is formed preliminarily across the entire semiconductor channel layer before the source/drain terminals are created. This preliminary formation ensures uniform surface preparation and low contact resistance across all regions. Subsequent selective removal then creates the final contact pattern, allowing the preliminary action to benefit the entire structure uniformly.
2Reliability
If a binary oxide layer is formed between the semiconductor channel layer and source/drain terminals, then contact resistance is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The formation of the binary oxide layer is merged with existing manufacturing steps. The layer is deposited using standard CVD or ALD processes that are already part of the semiconductor fabrication toolkit. The selective removal is integrated into the patterning sequence, combining multiple functions into unified process steps rather than adding entirely separate operations.
Solution Approach 2:
The binary oxide layer is formed by adjusting deposition parameters (such as oxygen partial pressure or precursor flow ratios) during existing CVD or ALD processes, rather than requiring entirely new equipment or methods. This parameter-based approach allows the same manufacturing tools to produce the specialized layer, minimizing the increase in process complexity.
3Reliability
If the binary oxide layer is formed across the entire semiconductor channel layer, then contact resistance is uniformly reduced, but subsequent processing steps increase
Solution Approach 1:
The binary oxide layer is rapidly deposited as a thin film using optimized CVD or ALD cycles, minimizing the time spent in the deposition step. The subsequent selective removal process is designed to be fast, using etch conditions that quickly clear the oxide from contact regions without requiring prolonged processing. This rushing through of intermediate steps maintains productivity while achieving the desired uniform contact resistance.
Solution Approach 2:
While the binary oxide layer is initially formed uniformly across the entire semiconductor channel layer to ensure consistent contact properties, subsequent selective removal creates local variations where the oxide is present or absent based on contact requirements. This local quality approach allows uniform benefits in regions needing low contact resistance while removing the layer in regions where direct contact is desired, optimizing both uniformity and productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The binary oxide layer effectively lowers contact resistance and improves the performance of semiconductor devices by modulating surface characteristics and facilitating better electrical connections.
Implementation Method 1
formed through deposition processes like CVD or ALD
Implementation Method 2
formed through deposition processes like CVD or ALD
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a semiconductor layer and a gate structure located on the semiconductor layer. The semiconductor device has source and drain terminals disposed on the semiconductor layer, and a binary oxide layer located between the semiconductor layer and the source and drain terminals.