Vertical Fin BJT Structure for High-Density Low-Leakage Semiconductors
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Solution Overview
Problem
As semiconductor devices shrink in size and design rule, their operating characteristics deteriorate, necessitating improved performance through high integration schemes, such as the use of multi-bridge channel field effect transistors and bipolar junction transistors, but existing technologies face challenges in maintaining electrical performance and reducing leakage current.
Innovation Solution
A semiconductor device design featuring a well area with impurity-implanted regions of different conductivity types, fin structures, epitaxial patterns, and specific contact arrangements, which form a vertical bipolar junction transistor configuration without a collector, enhancing current density and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOS field effect transistor size is reduced to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar MOSFET architecture to vertical bipolar junction transistor architecture, utilizing the vertical dimension to achieve high integration density while maintaining excellent electrical characteristics. The vertical structure allows current flow perpendicular to the substrate, enabling compact footprint without sacrificing performance
Solution Approach 2:
The patent employs selective impurity implantation to create regions with different conductivity types (n-type and p-type) within the semiconductor substrate. By controlling dopant concentration and distribution, the device achieves optimized electrical characteristics including high current density and low leakage current
2Device complexity
If vertical bipolar junction transistor is formed without collector, then device complexity is reduced, but electrical performance may deteriorate
Solution Approach 1:
The patent extracts the collector component from the traditional three-terminal BJT structure, creating a two-terminal vertical bipolar transistor. The collector function is integrated into the substrate, eliminating the need for a separate collector structure while maintaining electrical performance through optimized emitter and base region design
Solution Approach 2:
The patent merges the collector function into the substrate by forming the emitter and base regions directly in the semiconductor substrate. This integration maintains the essential bipolar transistor operation (injection and collection of carriers) while simplifying the overall device structure
3Area of stationary object
If impurity-implanted areas are arranged in specific patterns, then PN junction area increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the impurity-implanted regions into distinct emitter and base areas with specific conductivity types. By dividing the doped regions into functionally separate zones with controlled geometries, the design achieves large total PN junction area while managing manufacturing precision through standardized patterning processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves electrical performance by increasing the area of the PN junction and contact areas, leading to higher current density and reduced leakage current, while maintaining the performance of the vertical bipolar junction transistor even without a collector.
Implementation Method 1
one or more impurity-implanted areas in the well area, wherein the one or more impurity-implanted areas have a second conductivity-type different from the first conductivity-type
Implementation Method 2
the first fin structure includes first semiconductor patterns and first sacrificial patterns alternately stacked
Data Source
AI summary
A semiconductor device is provided. The semiconductor includes at least one of a well area in a substrate and having a first conductivity-type; impurity-implanted areas in the well, and having a second conductivity-type different from the first conductivity-type and arranged in a first direction, a first fin structure on the impurity-implanted area and having the second conductivity-type, wherein the first fin structure includes first semiconductor patterns and first sacrificial patterns alternately stacked; a first contact on the first fin structure; a first epitaxial pattern on the well area and having the first conductivity-type; and a second contact on the first epitaxial pattern.