Back-Side Conductive Layer Self-Alignment via Polymer Trenches
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Solution Overview
Problem
The existing semiconductor manufacturing processes require multiple costly lithographic steps to align back-side and front-side conductive layers, leading to complexity and inefficiency in the separation of semiconductor chips.
Innovation Solution
A method involving partial dicing of the substrate wafer to form trenches, filling these with a polymer material, and then applying a conductive layer on the back-side to create self-aligned insular islands of conductive material, which are separated by a polymer structure, allowing for chip separation without additional wet chemical etching and minimizing lithographic processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithographic processes are used to align back-side and front-side conductive layers, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies preliminary action by forming the back-side conductive layer pattern before substrate thinning, using the front-side conductive layer as a template. This preliminary patterning eliminates the need for subsequent lithographic alignment processes, resolving the contradiction between manufacturing precision and process complexity by establishing the conductive pattern early in the manufacturing sequence when the substrate is still in its wafer form
Solution Approach 2:
The front-side conductive layer serves as a self-aligned template for creating the back-side conductive layer pattern. The manufacturing process uses the existing front-side pattern to define the back-side pattern through direct transfer or alignment-free deposition, making the system self-service by eliminating external alignment references and reducing process complexity while maintaining precision
2Manufacturing precision
If multiple lithographic processes are used to align conductive layers, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The back-side conductive layer pattern is formed preliminarily before substrate thinning and chip separation. By establishing the conductive pattern on the intact substrate wafer using the front-side layer as a template, the process eliminates multiple time-consuming lithographic steps that would otherwise be required after chip separation, thereby reducing total manufacturing cycle time while maintaining alignment precision
Solution Approach 2:
The patent merges the back-side conductive layer formation process with the front-side conductive layer patterning process. By performing both patterning operations in sequence without intermediate lithographic steps, and by using the front-side pattern as a direct template for the back-side pattern, the manufacturing process combines multiple operations into a streamlined sequence, reducing both time and complexity
3Manufacturing precision
If wet chemical metal etching process is used to remove back-side metal layer, then manufacturing precision is improved, but device complexity and use of harmful substances increase
Solution Approach 1:
The patent extracts and eliminates the wet chemical etching step from the manufacturing process. By forming isolated islands of conductive material on the back-side during the preliminary patterning stage, the process removes the need for subsequent chemical etching to separate metal layers, thereby eliminating harmful chemical waste while maintaining precise separation through the physical isolation of conductive islands
Solution Approach 2:
The patent uses a temporary polymer structure during the patterning process that is removed after serving its alignment and isolation function. This disposable polymer template enables precise conductive layer formation without requiring harmful chemical etchants, as the polymer can be removed by simpler means, reducing chemical waste while maintaining manufacturing precision
Data Source
AI summary
A substrate wafer arrangement includes a substrate layer having a first main side and a second main side opposite the first main side, the first main side being a front-side and the second main side being a back-side, the substrate layer further having a plurality of semiconductor chips. A polymer structure arranged between the plurality of semiconductor chips extends at least from the front-side of the substrate layer to the back-side of the substrate layer and protrudes from a back-side surface of the substrate layer. The polymer structure separates a plurality of insular islands of conductive material, each insular island corresponding to a respective semiconductor chip of the plurality of semiconductor chips. Semiconductor devices produced from the substrate wafer arrangement are also described.