Back-Side Patterning Using Carrier Wafer Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current back-side patterning methods for silicon wafers in power devices, such as RC-IGBTs, require special apparatuses and processes, leading to high manufacturing costs and limitations in device properties and thickness, making mass production of thin silicon wafers challenging due to the need for specific alignment methods and carrier substrates.
Innovation Solution
A method involving the formation of deep trenches on the front side of the silicon wafer as alignment marks, followed by polishing to expose these marks on the back side, allowing for alignment and patterning without requiring special back-side lithography apparatuses or processes, using compatible front-side equipment and conditions, and employing a carrier wafer for thickness reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If infrared light alignment method is used for back-side patterning, then alignment can be achieved, but the process must be carried out in fixed steps and requires extremely high requirements on dopant type and concentration, severely limiting device properties and process conditions
Solution Approach 1:
The patent introduces a carrier wafer as an intermediary substrate. The carrier wafer is bonded to the front side of the silicon wafer, allowing the silicon wafer to be flipped and processed on the back side using standard front-side lithography equipment. This mediator enables back-side patterning without requiring specialized infrared alignment apparatus or imposing strict requirements on dopant characteristics.
Solution Approach 2:
The patent inverts the conventional back-side alignment approach. Instead of using special apparatus to align marks on the front side while the wafer is flipped, the method bonds the wafer to a carrier, flips it, and uses the carrier as a new reference frame. This allows standard front-side lithography tools to be used for back-side patterning, eliminating the need for expensive specialized equipment and relaxing dopant requirements.
2Measurement precision
If visible light reflection alignment is used, then alignment can be achieved, but holes must be drilled in the wafer stage to introduce light, increasing the complexity of circuit layout design
Solution Approach 1:
The carrier wafer serves as an intermediary that eliminates the need for complex wafer stage modifications. By bonding the silicon wafer to the carrier and flipping the assembly, the back side becomes accessible to standard lithography light sources without requiring holes or modifications to the wafer stage structure.
3Ease of manufacture
If special back-side lithography apparatuses are employed, then back-side patterning can be performed, but the manufacturing cost increases significantly
Solution Approach 1:
The patent makes existing front-side lithography apparatuses multi-functional by using them for both front-side and back-side patterning. The carrier wafer technique allows standard equipment to perform back-side processing after the wafer is flipped and bonded, eliminating the need for expensive specialized back-side lithography apparatus and significantly reducing manufacturing costs.
4Length of moving object
If carrier substrates made of organic materials or glasses are used for thin wafer processing, then thickness reduction is enabled, but electrostatic adsorption apparatuses must be substituted with special suction apparatuses
Solution Approach 1:
The patent changes the material parameter of the carrier substrate to silicon, which has the same electrostatic properties as the silicon wafer being processed. This allows thin wafers to be processed on carrier substrates while maintaining compatibility with existing electrostatic adsorption apparatuses, avoiding the need to substitute with special suction apparatuses required for organic or glass carriers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces production costs, enables compatible processing with existing thin-wafer techniques, and allows for effective double-sided patterning without the need for expensive special apparatuses, facilitating the production of thin silicon wafers with reduced thickness.
Implementation Method 1
bonding the front side of the silicon wafer with a carrier wafer
Implementation Method 2
polishing a back side of the silicon wafer until a thickness of at least a central portion of the silicon wafer is reduced to the target thickness
Data Source
AI summary
A method of back-side patterning of a silicon wafer is disclosed, which includes: depositing a protective layer on a front side of a silicon wafer; forming one or more deep trenches through the protective layer and extending into the silicon wafer by a depth greater than a target thickness of the silicon wafer; flipping over the silicon wafer and bonding the front side of the silicon wafer with a carrier wafer; polishing a back side of the silicon wafer; performing alignment by using the one or more deep trench alignment marks and performing back-side patterning process on the back side of the silicon wafer; and de-bonding the silicon wafer with the carrier wafer.