Back-Side Power Distribution Network for Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently distributing power due to the need for high aspect ratio contact etching, which increases production costs and technical difficulties.
Innovation Solution
A semiconductor device with a Back-Side Power Distribution Network (BSPDN) that directly supplies power to the transistors of the peripheral circuit unit, eliminating the need for high aspect ratio contact etching by using a buried power interconnection that penetrates the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional power distribution method is used requiring high aspect ratio contact etching, then power can be supplied to control circuits, but production cost increases and technical difficulty increases
Solution Approach 1:
The patent inverts the traditional power distribution approach by supplying power from the back side of the substrate rather than through front-side high aspect ratio contacts. The power interconnection structure extends from the back surface through the substrate to reach control circuits, eliminating the need for difficult high aspect ratio etching while maintaining reliable power delivery.
Solution Approach 2:
The patent transitions from a two-dimensional front-side power distribution to a three-dimensional approach by utilizing the back side of the substrate as an additional dimension for power entry. This allows power interconnections to approach control circuits from a different spatial direction, avoiding the constraints of front-side contact geometry.
2Reliability
If traditional power distribution method is used requiring high aspect ratio contact etching, then power can be supplied to control circuits, but technical complexity increases
Solution Approach 1:
The patent inverts the traditional power distribution approach by supplying power from the back side of the substrate rather than through front-side high aspect ratio contacts. The power interconnection structure extends from the back surface through the substrate to reach control circuits, eliminating the need for difficult high aspect ratio etching while maintaining reliable power delivery.
3Reliability
If long power transmission path is used, then power distribution can be achieved, but power consumption increases and current resistance increases
Solution Approach 1:
The patent performs preliminary routing of the power interconnection structure during substrate fabrication, embedding the power path optimization before device assembly. By pre-planning the power distribution routes from the back side, the design minimizes transmission length and resistance while ensuring reliable power delivery to all control circuits.
Data Source
AI summary
A semiconductor device includes a first substrate; a memory cell array, a second substrate, and a back-side power distribution network. The memory cell array includes memory cells that are vertically stacked over the first substrate. The second substrate including a front side facing the memory cell array and a back side at a higher level than the front side. The second substrate further includes a plurality of control circuits for controlling the memory cells. The back-side power distribution network includes a power interconnection that penetrates the second substrate and supplies power to the control circuits from the back side of the second substrate. The memory cell array is electrically connected to the plurality of control circuits of the second substrate by a bonding structure.