Static Storage TRIZ Cases
- Memory Circuit Redundant Decoder Control for Repair Efficiency
Redundant decoder control circuit activates storage lines based on test addresses within the memory cell array.
- Memory Subsystem Recovery Management for Retired Super Management Units
The system recovers non-defective memory units from retired groups by applying program pulses, preventing excessive loss of usable media capacity.
- Dynamic Code Word Distribution Among Multiple Decoders
Channel control logic distributes code words from a buffer to available decoders based on real-time availability status.
- Semiconductor Gate Contact Plug Landing Pad Structure
A gate contact plug extends through a gate pad region into a pre-formed landing pad within a substrate insulating layer.
- Semiconductor Test Device Pattern Memory Segmentation
A semiconductor test device rewrites pattern memory during operation to reduce hardware requirements.
- ECC Engine Defect Detection via Test Syndrome Comparison
Test circuits compare syndromes against parity data to detect ECC defects without adding separate hardware.
- SSD Peer Group Data Protection Offload
A storage system uses SSD peer groups to offload data protection computations from the host CPU.
- Memory Module Interposer Thermal Isolation Design
Interposer separates memory chips from controller, reducing heat transfer and power consumption in AI systems.
- Back-Side Power Distribution Network for Semiconductor Devices
A back-side power distribution network supplies control circuits via a substrate-penetrating interconnection, eliminating high aspect ratio contact etching.
- Flash Memory Error Detection Protocol for Signal Integrity
Time-multiplexed error detection signals verify access control correctness, preventing data corruption from propagation delays at high operating frequencies.
- Memory Card Connector Interrupt Signal for Data Integrity
A memory card connector generates an interrupt signal upon removal to terminate operations before power loss.
- Memory Macro Bypass Paths for SRAM ECC Testing
Integrated bypass paths route test data through storage portions, reducing circuit complexity and test patterns.
- Split Output Shunt Regulator for RFID FRAM Stability
Split rectifier outputs isolate FRAM power delivery from discharge regulation, stabilizing voltage against temperature shifts and intermittent supply.
- DRAM ECC Counter Verification via Row Hammer Victim Selection
Test device selects a memory row as a victim through ping-pong row hammer effect to generate errors for ECC counter analysis.
- Voltage Regulator Dead Band Control for Stability and Power
A voltage regulator circuit uses a dead band region where the feedback loop remains inactive to reduce power consumption.
- Reference Bit Testing and Repair in Memory Built-In Self-Test
A memory-testing circuit compares data bit columns with reference bit columns to detect defects during read operations.
- In-Memory ECC Logic for Cross-Point Memory Compute
Local media access circuitry executes preliminary error correction on cross-point memory data, reducing bus transmission energy and processing time.
- Memory Row Remapping to Mitigate Bit Errors
A memory device remaps defective row indices to redundant rows, preserving logical address access.
- Redundancy Circuit Block Repair for Memory Defects
A redundancy circuit redirects defective data to a shared ECC array using non-volatile fuses.
- Hard Disk Platter Data Distribution for Mechanical Failure Recovery
A hard disk controller distributes data blocks and redundancy parity across separate platter surfaces to enable physical failure isolation.