Semiconductor Gate Contact Plug Landing Pad Structure
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Solution Overview
Problem
There is a growing demand for semiconductor devices with increased data storage capacity, and existing technologies have limitations in enhancing productivity and electrical characteristics, particularly in three-dimensionally arranged memory cells.
Innovation Solution
The semiconductor device includes a first semiconductor structure with a substrate, circuit devices, and a lower interconnection structure, and a second semiconductor structure with a substrate having regions, a substrate insulating layer, gate electrodes, and gate contact plugs that extend through the gate pad regions and into a landing pad, optimizing the structure for improved productivity and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The device is divided into two separate semiconductor structures: a first structure containing circuit devices and lower interconnection, and a second structure containing vertically stacked memory cells with gate electrodes. This segmentation allows independent optimization of each structure, reducing overall device complexity while maintaining high storage capacity through the 3D arrangement in the second structure.
Solution Approach 2:
The memory cells are arranged in a three-dimensional vertical stack in the second semiconductor structure, with gate electrodes stacked in the first direction and extending in the second direction. This dimensional transition from 2D to 3D arrangement increases storage capacity without proportionally increasing planar footprint or process complexity.
2Reliability
If gate contact plugs extend through gate pad regions into landing pads, then electrical connections are improved, but manufacturing precision requirements increase
Solution Approach 1:
The landing pad is formed in advance within the substrate insulating layer, creating a pre-positioned electrical connection point. The gate contact plug then extends from the gate pad region through the substrate insulating layer to connect with this pre-formed landing pad, ensuring reliable electrical connection while simplifying the manufacturing process by establishing connection points before final plug formation.
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
A semiconductor memory device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer extending through the second substrate; a landing pad extending through the substrate insulating layer; gate electrodes spaced apart from each other and stacked on the first region in a first direction and extending with different lengths in a second direction on the second region, each of the gate electrodes including a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending through the gate pad region of at least one of the gate electrodes and into the landing pad. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure.