DRAM ECC Counter Verification via Row Hammer Victim Selection
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Solution Overview
Problem
Conventional methods face challenges in verifying the error correction and checking (ECC) functions in dynamic random access memory (DRAM), particularly in accurately testing the ECC counter, which increments error counts and requires reliable scrub operations.
Innovation Solution
A test device and method that selects a memory row as a victim row through a ping-pong row hammer effect, performs multiple error correction scrub (ECS) operations, and compares the addresses recorded in mode registers with the selected row to generate a test result, ensuring the ECC counter functions correctly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional ECC verification methods are used, then the testing process is simple, but the measurement precision of ECC counter functionality is insufficient
Solution Approach 1:
The patent introduces a test device as an intermediary system between the memory device and the verification process. This test device includes a controller that manages the complex testing operations, allowing accurate ECC counter verification without requiring the memory device itself to be overly complex. The test device mediates the interaction between test stimuli and ECC counter responses.
Solution Approach 2:
The test device performs preliminary actions by first inducing row hammer effects and triggering ECS operations before measuring the ECC counter values. This preliminary preparation ensures that the ECC counter is in a known state and has been properly stimulated, enabling accurate subsequent measurement without requiring complex real-time monitoring during normal operation.
2Reliability
If row hammer effect is used to induce errors, then the ECC counter can be tested, but the difficulty of detecting and measuring increases
Solution Approach 1:
The test device implements feedback by reading back the contents of mode registers that contain information about which row was identified as the victim row by the ECC counter. This feedback mechanism allows the test device to verify whether the ECC counter correctly identified the row that should have accumulated the most errors from the row hammer effect, thereby enabling reliable detection without excessive complexity.
Solution Approach 2:
The patent replaces direct physical measurement of error counts with a substitution approach: instead of directly measuring the victim row identification, the system substitutes reading and comparing mode register values. This substitution simplifies the detection process by using software-readable registers rather than complex hardware measurement circuits.
3Measurement precision
If multiple ECS operations are performed, then the ECC counter accuracy is improved, but the loss of time increases
Solution Approach 1:
The test device employs periodic action by performing multiple ECS operations in sequence, with each operation contributing to the accuracy of the ECC counter measurement. Rather than attempting to achieve accuracy in a single operation, the system uses repeated periodic ECS operations to build up statistically significant error counts, then reads the final result efficiently to minimize total testing time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively tests the ECC counter by accurately identifying the row with the highest error count, determining whether the ECC counter passes or fails, thereby ensuring reliable error correction and checking functionality in DRAM.
Implementation Method 1
making a selected memory row of the memory device to be a victim row by a row hammer effect
Data Source
AI summary
A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.